Karthik Vasanth

Automatic synthesis of equipment recipes from specified wafer-state transitions

Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions. We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer.

Predictive BSIM3v3 modeling for the 0.15-0.18 /spl mu/m CMOS technology node: a process DOE based approach

An efficient and accurate approach using the BSIM3v3 compact model to support concurrent process technology development and circuit design is presented. The key feature is the ability to generate accurate pre-silicon BSIM3 models for new technologies taking into account process information from existing technologies. Device, circuit and process optimization results are presented.

Challenges and considerations of analog front-ends design for portable ultrasound systems

High performance portable ultrasound imaging system is demanded by a wide variety of point of care applications. Ultrasound system minimization and improvement have been proven in the past several years. One of the main driving forces for portable ultrasound system minimization and improvement is the advanced semiconductor technology. Besides, transducer technology is further enhancing system sensitivity and reducing system cost. Corresponding silicon processes were selected for achieving low power, low noise and compact size in ultrasound analog front-end (AFE) design. The combination of bipolar and CMOS processes achieves significant power, noise and size reduction, as well as superior CW performance. Key considerations of ultrasound analog front-end were discussed and analyzed. Standard test procedures were developed to assist the design.

The effect of deterministic spatial variations in retrograde well implants on shallow trench isolation for sub-0.18 /spl mu/m CMOS technology

The high energy retrograde well implants for sub-0.18 microns CMOS are done at a normal or near normal incidence to minimize the shadowing due to the thick photoresist edges. The endstation geometry in a high energy implanter results in an incident angle variation across the wafer, which causes strong spatial variations in the well profile and can negatively impact device performance. We show that the spatial variations can have significant impact on shallow trench isolation (STI), by causing in a deterministic pattern the failure of STI devices on a wafer. These spatial variations are important and need to be taken into consideration for STI design.

An efficient method for modeling the effect of implant damage on NMOS devices using effective profiles and device simulation

This paper presents a phenomenological model to account for the channel boron redistribution in NMOS devices caused by implant damage during source drain processing. The model parameters are determined using device I-V characteristics for various channel and source drain implant conditions and can be used to extract effective 2D dopant profiles. The approach presented in this paper allows device simulation at various gate lengths without the need for calibrating simulation parameters at every gate length. Advantages and limitations of the proposed method are also discussed.

A 180-V pp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology

This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7- μm CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 Vpp, and a second-order harmonic distortion (HD2) of -56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle.

An application of process synthesis methodology for first-pass fabrication success of high-performance deep-submicron CMOS

This paper describes a methodology to reduce the time and cost of developing deep sub-micron semiconductor manufacturing technology. The methodology consists of following the components: compact models for device performance and reliability, compact models for process modules, and synthesis algorithms that allow the rapid exploration of large design spaces to identify all device and process flow designs that meet the device specifications. This approach is illustrated by applying it to the design of CMOS gate shrinks from 0.35 /spl mu/m to 0.29 /spl mu/m drawn poly gate length. The synthesized devices were manufactured, meeting all performance and reliability requirements in the first silicon run.

Application based reliability assessment and qualification methodology for medical ICs

Reliability assessment and qualification system has strong economic implications for both manufacturers and customers. The best system should have a good balance among cost of verification, market timing requirement, and acceptable risk that meets the targeted users application conditions and requirements. With the increasing use of innovative electronics in the medical applications, it becomes difficult to have a single reliability assessment and qualification approach to serve all applications. In this paper, we review the existing reliability assessment and qualification framework, and discuss their applicability in medical ICs. We will discuss the tradeoff and challenges in defining reliable medical IC products based on the application demands using a couple of medical IC examples.

Statistical aspects of tuning simulators to noisy data

The purpose of TCAD tools is to reduce the cost of developing new semiconductor technologies by replacing real wafers with simulations. If the process flows and device structures can be simulated accurately, then new device designs can be analyzed using simulations instead of real wafers. However, due to uncertainty in material coefficients and deficiencies in the physical models, process and device simulators often fail to provide the accuracy necessary for predictive device design, thereby limiting the impact of TCAD on device development cost. To address this problem, process and device simulators are often tuned to match experimental data, i.e. the simulator coefficients are adjusted such that the simulator outputs match experimentally measured data. However, the experimental data to which the simulators are tuned contain noise due to both process variation and measurement noise. Since tuning parameters are adjusted such that the simulator outputs, which are deterministic, match the experimental data, the uncertainty in the data implies uncertainty in the optimal values of the tuning parameters. This paper presents a methodology for tuning to uncertain and sparse experimental data and estimating the tuning parameter distribution based on the experimental data uncertainty. This distribution can be used to determine whether there is enough data to generate confidence in the optimal values of the tuned parameters. Additionally, we show how the tuned parameter distribution can be used to estimate the uncertainty in simulations conducted at conditions other than those used for tuning.

Methods for the design of microelectronic devices and process flows for manufacturability

Small feature sizes and reduced tolerances of state-of-the-art microelectronic devices make them extremely sensitive to manufacturing variations. This paper describes two approaches dealing with manufacturing variations: process control and statistical design for manufacturability. Process control seeks to reduce the variability of each process module and statistical design seeks to minimize the impact of the variability. An example illustrates the use of process control to minimize variability. Then, a novel approach for statistical design and its application to statistical optimization of deep submicron CMOS is described. This approach is based on a Markov representation of a process flow that captures the sequential and stochastic nature of semiconductor manufacturing. Using this approach we have been able to predict the variability in device performance for a number of process flows. Transistor designs and process flows optimized using this approach show lower variation in key device performances on fabrication.