Qwai H. Low

Cu wire bonding for fine pitch 65nm silicon integrated circuits

Results of a development program aimed at introducing Cu wire to a low K circuit under pad integrated circuit made in 65nm technology are summarized. The results demonstrate that if the wire bond process is optimized along with the tool design, then it is possible to produce both substrate (PBGA) and lead frame (TQFP) devices with pure Cu wire that show no evidence of damage to the underlining dielectric stack, robust ball bonds and stitch bonds with no evidence of lifts or cracks. Furthermore, the data demonstrate that the fundamental reliability of both packages as determined by temperature cycling, high temperature humidity storage and high temperature storage is more than sufficient if the correct mold compound is used.

Bonding copper low-k die with bond pads over active circuitry (pads on I/O)

Summary form only given. As the demand for smaller die with high input/output (I/O) connections continues to rise, new innovations on die bond pad placement and design are required. Some of LSI Logics customers are currently requesting die with as many as 1200 bonding pads on an 8 mm die. To meet customer requirements as well as enhancing die technology, LSI Logic has developed an innovative way of increasing die bond pad density without increasing the die size by putting bond pads over active circuitry on low-k copper die. Moreover, this new innovation can also be used to increase I/O count while reducing the die size. LSI Logic refers to this new technology as pads on I/O. The challenges presented in bonding low-k die are well documented. These challenges include, but are not limited to, pad metal cracking, pad metal lifting on the copper/low-k, delamination in low-k layers, and changes in the I/O electrical parametric performance. Before die fabrication, the electrical impact of locating the pads over I/O was evaluated. Additionally, finite element analysis was also performed on the new pad structures to determine the impact of mechanical forces due to the bonding forces and thermal loads due to the epoxy materials (die attach/mold compound) used. The parameters obtained from these evaluations were used to develop a suitable test design vehicle that is capable of evaluating most of the major failures that are involved in assembly and test of low-k die with pads on I/O. Test chips with range of 3 to 8 metal layers were fabricated using black diamond low-k. The dies were assembled on a 14/spl times/20 mm 64 PQFP and 35mm 492 PBGA using special low stress molding compound and die attach epoxy. In order to obtain a suitable bonding parameter window, a 9-leg design of experiment (DOE) was performed using the ball shear test (BST), the ball pull test (BPT), and the pad-cratering test (PCT) as the input parameters. Additionally, bond pad cross sections were evaluated to determine the presence of cracks in the underlying copper metallization and low-k dielectric layers. From the DOE analysis, optimized bonding parameters (power, force, time, & temperature) were determined. The optimized parameters were used in the assembly of qualification units. The assembled units were subjected to a JEDEC level 3 qualification in which temperature cycling condition B (TCB), biased temperature humidity (BTH), and high temperature operation life (HTOL) tests were performed to induce failures. Electrical tests and acoustic microscopy (SONOSCAN) was performed on the units to determine the presence of opens/shorts/delamination in the units. HSPICE was also used to compare the parametric shifts between standard low-k die with peripheral pads and the new design with wire pads on I/O. From the test data, it is observed that the wirebond production monitors (BST, BPT, and PCT) were easily satisfied. Package cross-section pictures taken by an SEM does not indicate damage in the underlying layers. In addition, it is found from HSPICE evaluation that there are no shifts in the monitored I/O leakage electrical data. Currently, LSI Logic is in full production with copper low-k pads on I/O die. These die are fabricated with 3-rows of staggered bonding pads which are all located on the active circuitry. This has resulted in approximately 40 percent reduction in die size for high pin-count wire bonded packages.