Ravneet Kaur

TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (NA), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.

Two-dimensional analytical model to characterize novel MOSFET architecture: insulated shallow extension MOSFET

In this paper, a computationally efficient model using evanescent mode analyses for solving two-dimensional Poissons equation in the channel region has been presented for an accurate prediction of (a) surface potential, (b) electric field, (c) IDS–VGS characteristics, (d) threshold voltage, (e) transconductance and (f) drain conductance of insulated shallow extension MOSFET. The important short channel device features, drain induced barrier lowering (implemented via the voltage doping transformation method), channel length modulation and velocity saturation/overshoot, have been included in the model in a physically consistent manner. The obtained analytical results have been verified by ATLAS 2D: device simulation software.

Hot-Carrier Reliability and Analog Performance Investigation of DMG-ISEGaS MOSFET

Dual-material-gate (DMG) insulated shallow extension gate-stack MOSFET involving dielectric pocket (DP) and DMG assimilation onto the conventional MOSFET has been studied. Simulations reveal a reduction in substrate leakage current, linearity improvement, enhancement in - g_m/I_DS, early voltage (V_EA), and g_m/g_d, down to 50-nm gate length as an outcome of this DP and DMG integration.

Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

Improvement in breakdown voltage (BVds) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length (L g ), but due to lithographic limitation, shortening L g below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate on to the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the BVds of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in BV ds can be obtained by applying field plates, especially at the drain side. The important parameters affecting BVds and cut-off frequency (f T ) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, Γ-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

Performance Investigation of 50-nm Insulated-Shallow-Extension Gate-Stack (ISEGaS) MOSFET for Mixed Mode Applications

An extended study of electrical characteristics of 50-nm single-material-gate insulated-shallow-extension-gate-stack (ISEGaS) MOSFET is performed using ATLAS-2D. Incorporation of dual-material-gate architecture leads to the suppression of short channel effects along with the improvement in device intrinsic gain (g_mtimesR_out), voltage gain (g_m/I_DS), and I_on/I_off ratio, thereby opening a new era of ISEGaS MOSFETs for mixed mode applications

On-state and RF performance investigation of sub-50 nm L-DUMGAC MOSFET design for high-speed logic and switching applications

In this paper, an extensive study on the on-state, switching and RF performance of a laterally amalgamated dual material gate concave (L-DUMGAC) MOSFET and the influence of technology variations such as gate length, negative junction depth (NJD) and gate bias on the devices behavior is performed using an ATLAS device simulator. Simulations reveal that the L-DUMGAC design exhibits a significant enhancement in the devices switching characteristics in terms of reduced on-resistance and, hence, the reduced conduction power loss, switching loss and enhanced on-current, ION. Further, the L-DUMGAC design is studied for the RF application circuit design by examining the stability, cut-off frequency, power gains and the parasitic capacitances. The results are, thus, useful for optimizing the performance and reliability of nanoscale L-DUMGAC MOSFETs for high-speed logic, switching and RF applications.

On-state and switching performance investigation of sub-50nm L-DUMGAC MOSFET design for high-speed logic applications

In this paper, an extensive study on the on-state and switching behavior of laterally amalgamated dual material gate concave (L-DUMGAC) MOSFET (Fig.l) is performed and the influence of technology variations, such as gate length, negative junction depth (NJD) and gate bias has been investigated using ATLAS device simulator.

Unified Subthreshold Model for Channel-Engineered Sub-100-nm Advanced MOSFET Structures

In this paper, a universal and computationally efficient subthreshold model for sub-100-nm nonuniformly doped channel MOSFET has been presented. The model incorporates drain-induced barrier lowering effect by means of the short-channel depletion width parameter d, which is evaluated using the voltage doping transformation method. The model can accurately predict the following: 1) surface potential; 2) electric field; 3) threshold voltage; and 4) subthreshold slope, for various lateral as well as transverse channel-engineered structures such as retrograde, graded channel, lightly doped drain (LDD), halo, and pocket implant technology for sub-100-nm channel length. In this paper, we have also proposed a novel device architecture incorporating the benefits of asymmetric halo and LDD doping. The analytical results have been verified by ATLAS 2-D device simulation software.

GEWE-RC MOSFET: A solution to CMOS technology for RFIC design based on the concept of intercept point

In this paper, the linearity performance of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET is investigated using ATLAS device simulator, based on the concept of intercept point. Further, the impact of various technological parameter variations, such as gate length (LG), negative junction depth (NJD), screening metal gate workfunction (PhiM2) and substrate doping (NA) on the linearity performance of GEWE-RC MOSFET, has been explored. Simulation results reveal that GEWE-RC MOSFET design exhibits significantly improved linearity characteristics, in comparison to the conventional Recessed Channel (RC) and bulk, based on third-order input intercept power (IIP3) desirable for RF and wireless communication designs.

Analytical approach for high temperature analysis of AlGaN/GaN HEMT

An analytical thermal model of AlGaN/GaN high electron mobility transistor (HEMTs) has been developed. This temperature dependent model incorporates the polarization effects at heterointerface. The model also accounts for the mobility degradation with increase in temperature, which is one of the major causes in deteriorating the driving current. By using the variation of band gap with temperature, the temperature dependence on threshold voltage, sheet carrier concentration and drain current is studied. Further, the temperature variation shows the applicability of the device in a variable thermal environment. The results show excellent agreement when compared with experimental data thereby proving the validity of the model.