Raghaw Rai

Thermodynamic stability of high-K dielectric metal oxides ZrO2 and HfO2 in contact with Si and SiO2

We present theoretical and experimental results regarding the thermodynamic stability of the high-k dielectrics ZrO2 and HfO2 in contact with Si and SiO2. The HfO2/Si interface is found to be stable with respect to formation of silicides whereas the ZrO2/Si interface is not. The metal–oxide/SiO2 interface is marginally unstable with respect to formation of silicates. Cross-sectional transmission electron micrographs expose formation of nodules, identified as silicides, across the polycrystalline silicon/ZrO2/Si interfaces but not for the interfaces with HfO2. For both ZrO2 and HfO2, the x-ray photoemission spectra illustrate formation of silicate-like compounds in the MO2/SiO2 interface.

Compatibility of polycrystalline silicon gate deposition with HfO2 and Al2O3/HfO2 gate dielectrics

Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO2 and Al2O3 capped HfO2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO2 results in electrical properties much worse compared to similar HfO2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al2O3 capped HfO2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness.

HfO2 Gate Dielectrics Deposited via Tetrakis Diethylamido Hafnium

HfO 2 films deposited via tetrakis diethylamido hafnium (TDEAH) precursor using MOCVD (metal organic chemical vapor deposition) are presented. TDEAH is a promising precursor candidate for the deposition of high permittivity gate dielectrics. We report the impact of process and annealing conditions on the physical and electrical properties of the film. Deposition and annealing temperatures influence the microstructure, density, and impurity levels of TDEAH HfO 2 films. Spectroscopic ellipsometry shows that film microstructure manifests itself in the optical properties of the film, particularly in the presence of a band edge related feature at 5.8 eV An impurity analysis using Auger electron spectroscopy, secondary ion mass spectroscopy, and Raman spectroscopy, indicates that carbon impurities from the precursor exist as clusters within the HfO 2 dielectric. The impact of deposition temperature and annealing temperature on the capacitance vs. voltage and current density vs. voltage characteristics of platinum gated capacitors is studied. Correlation of physical film properties with the capacitance and leakage behavior of the TDEAH HfO 2 films indicates that impurities, in the form of carbon clusters, and low HfO 2 film density are detrimental to the electrical performance of the gate dielectric.

Atomic layer deposition of HfO2 thin films and nanolayered HfO2–Al2O3–Nb2O5 dielectrics

Smooth, 4–6-nm thick hafnium oxide films were grown by atomic layer deposition from HfI4 or HfCl4 and H2O on SiO2/Si(1 0 0) substrates at 300 °C. Non-uniform films were obtained on hydrogen-terminated Si(1 0 0). The stoichiometry of the films corresponded to that of HfO2. The films contained small amounts of residual chlorine and iodine. The films deposited on SiO2/Si(1 0 0) were amorphous, but crystallized upon annealing at 1000 °C. In order to decrease the conductivity, the HfO2 films were mixed with Al2O3, and to increase the capacitance, the films were mixed with Nb2O5. The capacitance–voltage curves of the Hf–Al–O mixture films showed hysteresis. The capacitance–voltage curves of HfO2 films and mixtures of Hf–Al–Nb–O were hysteresis free.

Compatibility of Silicon gates with hafnium-based gate dielectrics

Silicon gate compatibility problems with hafnium-basd gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO2 at conventional temperatures (near 620°C) results in (1) a low density ot large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO2 films using metal gates or silicon gates with low temperature deposition. However, depositing conventional CVD poly-Si gates directly onto Al2O3-capped, hafnium-silicate-capped, or physical vapor deposition (PVD) silicon-capped HfO2 resulted in the absence of large inhomogeneous poly-Si grains and well behaved capacitors with leakage reduction greater than 103 times compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO2 are attributed to a partial reduction of the HfO2 by the poly-Si deposition ambient. In the first case (1) the partial reduction occurs locally on the HfO2 surface, forming Hf-Six bond(s) which act as nucleation points for crystalline silicon growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.

Theoretical and experimental investigation of boron diffusion in polycrystalline HfO2 films

We present ab initio modeling results including formation, migration, and activation energies for B diffusion through bulk and grain boundaries in polycrystalline HfO2 films. Modeling results clearly indicate that B can penetrate through a 40 A HfO2 film via grain boundary diffusion, but not by bulk diffusion. Secondary ion mass spectroscopy analysis of B concentration profiles for polysilicon/HfO2/Si gate stacks after different anneals showed double B peaks at the interfaces and thus confirmed the modeling prediction.

Specific site cross-sectional sample preparation using focused ion beam for transmission electron microscopy

Abstract Sample preparation using focused ion beam (FIB) for transmission Electron Microscopy (TEM) analysis was reviewed. Improving the quality of FIB prepared TEM sample has been an issue in the past. A specific site cross-sectional sample preparation method has been developed using FIB milling for TEM characterization of integrated circuits (ICs). Approach of front side and back side milling has been applied to thin the semiconductor samples for electron transparency. Back side milling has been applied for the first time in our TEM sample preparation using FIB milling. Proper tilting of the stage and use of low beam current are found to be critical for TEM samples quality. Samples prepared during present work are thinner, artifact-free, and of excellent quality for TEM analysis. It is possible to prepare specific site cross-sectional TEM samples of ICs within 2–3 hours using FIB milling. Some examples of specific site cross-sectional TEM analysis of Si based device structures are presented. Final achievable thicknesses of the samples are exemplified from the fact that atomic resolution imaging was possible and microstructure was seen in the tungsten plugs.

Evaluation of Candidate Metals for Dual-Metal Gate CMOS with HfO 2 Gate Dielectric

As the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 A equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO 2 as candidate metals for dual-metal gate CMOS using HfO 2 as the gate dielectric. The gate work-function was determined by fabricating MOS capacitors with varying dielectric thicknesses and different post-gate anneals. The metal-dielectric compatibility and thermal stability was studied by annealing the stacks at different temperatures. The gate stacks were characterized using TEM, SIMS and X-ray diffraction. Based on workfunctions and thermal stability, TaSiN and TaN show most promise as metal electrodes for HfO 2 n-MOSFETs.

Surface and Interface Roughness of Ultrathin Nitric Oxide Oxynitride Gate Dielectric

Surface and interface roughness of 40-A oxynitride films grown on preoxidized (100) silicon surfaces in a nitric oxide (NO) ambient at 800°C have been investigated using atomic force microscopy with power spectral density, and cross-sectional transmission electron microscopy measurements. The results showed that the NO oxynitride surface is smoother and has less interfacial roughness compared to the thermal oxide (without NO anneal). These results are important given the current technological interest in oxynitrides for ultrathin gate dielectric applications.

High K LAON for gate dielectric application

A promising high k material, lanthanum aluminum oxynitride (LAON), with excellent material and electronic properties is reported. The LAON film has good thermal stability and CMOS process compatibility at 1000 C. The LAON material has a dielectric constant of above 20, bandgap of 6.6 eV. Well-behaved I-V and C-V were obtained for 80 A LAON on silicon.