John M. Grant

Compatibility of polycrystalline silicon gate deposition with HfO2 and Al2O3/HfO2 gate dielectrics

Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO2 and Al2O3 capped HfO2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO2 results in electrical properties much worse compared to similar HfO2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al2O3 capped HfO2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness.

Dual-metal gate CMOS with HfO 2 gate dielectric

We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).

80 nm poly-Si gate CMOS with HfO/sub 2/ gate dielectric

We report here for the first time the formation of an amorphous oxide layer between the polysilicon gate and hafnium oxide (HfO/sub 2/) gate dielectric due to a lateral oxidation mechanism at the gate edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv of 25 /spl Aring/ with a leakage current 1000/spl times/ lower than SiO/sub 2/ was obtained for a 30 /spl Aring/ HfO/sub 2//12 /spl Aring/ interfacial oxide stack. In this paper, we present results on the physical and electrical characterization.

Compatibility of Silicon gates with hafnium-based gate dielectrics

Silicon gate compatibility problems with hafnium-basd gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO2 at conventional temperatures (near 620°C) results in (1) a low density ot large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO2 films using metal gates or silicon gates with low temperature deposition. However, depositing conventional CVD poly-Si gates directly onto Al2O3-capped, hafnium-silicate-capped, or physical vapor deposition (PVD) silicon-capped HfO2 resulted in the absence of large inhomogeneous poly-Si grains and well behaved capacitors with leakage reduction greater than 103 times compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO2 are attributed to a partial reduction of the HfO2 by the poly-Si deposition ambient. In the first case (1) the partial reduction occurs locally on the HfO2 surface, forming Hf-Six bond(s) which act as nucleation points for crystalline silicon growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.

Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]

We have examined the impact of small and systematic changes at the metal/dielectric interface on metal work-function and report on Fermi level pinning of TaN, TaSiN and TiN gates on SiO/sub 2/, Al/sub 2/O/sub 3/ and HfO/sub 2/ for the first time. The shifts in work-function agree in most cases with the MIGS theory if accurate theoretical parameters are used.

Impact of photoresist taper and implant tilt angle on the interwell isolation of subquarter-micron CMOS technologies

The impact of photoresist taper and implant tilt angle on the interwell isolation of a sub-0.25 micrometer CMOS technology is investigated. It is shown that as the trench depth is decreased and the n-well dose and energy is increased, interwell isolation below 1 micron N+/P+ spacing is degraded. The reduction of photoresist taper is shown to be a key factor in improving interwell isolation and decreasing MOSFET device parasitics. By optimizing the photoresist process to minimize taper, acceptable N+/P+ isolation is achieved down to 0.7 micrometers. Also, by utilizing a two dimensional interwell isolation test structure, it is found for the first time that as the interwell isolation is scaled into the sub-micron regime, lateral n-well dopant displacement caused by the implant tilt angle can result in reduced overlay margin.

Performance, standby power, and manufacturability trade-off in transistor design consideration for 0.25-μm technology

In this paper, we compare four different approaches for transistor design for the 0.25 micrometer technology from the point of view of performance, stand-by power and ease of manufacturing. For the high performance logic applications such as high end microprocessors, 0.18 micrometer transistor (Lgate equals 0.18 plus or minus 0.02 micrometer) with super steep retrograde wells and halo implants but without extension implants can achieve maximum frequency of operation (Fmax) exceeding 380 Mhz for the 0.25 micrometer technology. On the other hand, for low power applications such as mobile communication equipments, a different 0.22 micrometer (Lgate equals 0.22 plus or minus 0.02 micrometer) transistor design which simplifies manufacturing process by eliminating two photolithography steps becomes more attractive. The four transistor designs are compared using CV/I metric and manufacturability trade-offs are discussed.