Raghuveer Patlolla

Tungsten and cobalt metallization: A material study for MOL local interconnects

Middle-of-the-line (MOL) interconnect and contact resistances represent significant impacts to high-end IC performance at ≤ 10 nm nodes. CVD W-based metallization has been used for all nodes since the inception of damascene. However, it is now being severely challenged due to limited scaling of the traditional PVD Ti/CVD TiN barrier and ALD nucleation layers. This study reports the use of alternate barriers, along with metal-to-metal contact interface cleans, to reduce contact resistance for W-based MOL metallization. As well, we report the first use of Co metal for MOL contacts and local interconnects, with successful integration below a Cu BEOL dual damascene V0/M1 module. Metal line resistances are compared among the various options, and the challenges with each option are highlighted.

Experimental study of nanoscale Co damascene BEOL interconnect structures

We characterize integrated dual damascene Co and Cu BEOL lines and vias, at 10 nm node dimensions. The Co to Cu line resistance ratios for 24 nm and 220 nm wide lines were 2.1 and 3.5, respectively. The Co via resistance was just 1.7 times that of Cu, with the smaller ratio attributed to the barrier layer series via resistance. Electrical continuity of Co via chain structures was good, while some chain-chain shorts and leakage suggests metal residuals from the Co polish process. The Co lines and vias, fabricated using conventional BEOL processes, exhibit good Co fill by TEM, with no visible evidence of Co in the dielectric. The relatively smaller resistance increase for Co vias suggests a potential via resistance benefit, a thinner or less resistive barrier can be employed. Co line resistance will likely not be competitive with Cu until after the next technology node.

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

BEOL process integration for the 7 nm technology node

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.

Ruthenium interconnect resistivity and reliability at 48 nm pitch

48 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Ru interconnect has comparable high yield for line and via macros. Electrical results show minimal impact for via resistance and around 2 times higher line resistance. Resistivity and cross section area of Ru interconnects are measured by temperature coefficient of resistivity method and the area was verified by TEM. Reliability results show non-failure in electromigration and longer time dependent dielectric breakdown. Based on the data collected, Ru could be a metallization contender at linewidth of 16 nm and below.

CVD-Co/Cu(Mn) integration and reliability for 10 nm node

In studying integrated dual damascene hardware at 10 nm node dimensions, we identified the mechanism for Co liner enhancement of Cu gap-fill to be a wetting improvement of the PVD Cu seed, rather than a local nucleation enhancement for Cu plating. We then show that Co “divot” (top-comer slit void defect) formation can be suppressed by a new wet chemistry, in turn eliminating divot-induced EM degradation. Further, we confirm a relative decrease in Cu-alloy seed proportional resistivity impact compared to scattering at scaled dimensions, and finally we address the incompatibility between the commonly-used carbonyl-based CVD-Co process with Cu-alloy seed EM performance This problem is due to oxidation of Ta(N) barriers at the TaN/CVD-Co interface by carbonyl-based CVD processes, which then consumes alloy atoms before they can segregate at the Cu/cap interface. We show that O-free CVD-Co may solve this problem. The above solutions may then enable CVD-Co/Cu-alloy seed integration in advanced nodes.

Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes

Through-Co self-forming-barrier (tCoSFB) metallization scheme is introduced, with Cu gap-fill capability down to 7 nm-node dimensions. Mn atoms from doped-seedlayer diffuse through CVD-Co wetting layer, to form TaMnxOy barrier, with integrity proven by vertical-trench triangular-voltage-sweep and barrier-oxidation tests. tCoSFB scheme enables 32% and 45% lower line and via resistance, respectively at 10 nm node dimensions, while achieving superior EM performance to competitive TaN/Co and TaN/Ru-based barriers.

Performance of ultrathin alternative diffusion barrier metals for next - Generation BEOL technologies, and their effects on reliability

In order to maximize Cu volume and reduce via resistance, barrier thickness reduction is a strong option. Alternative barriers for next-generation BEOL were evaluated in terms of barrier performance to O2 and Cu diffusion, and effects on reliability. A clear correlation of O2 barrier performance to electromigration was observed, suggesting that the key role of the barrier layer is to prevent oxidation of Cu or the Cu/barrier interface. Long-throw PVD-TaN showed superior O2 barrier performance to alternative metals such as PEALD-TaN, thermal ALD-TaN, -TaN(Mn) and - MnN and MnSiO3 self-forming barrier.

Electromigration and resistivity in on-chip Cu, Co and Ru damascene nanowires

Electromigration and resistivity of Cu, Co and Ru on-chip interconnection have been investigated. A similar resistivity size effect increase was observed in Cu, Co, and Ru. The effect of liners and cap, e.g. Ta, Co, Ru and SiCxNyHz, on Cu/interface resistivity was not found to be significant. Multilevel Cu, Co or Ru back-end-of-line interconnects were fabricated using 10 nm node technology wafer processing steps. EM in 22 nm to 88 nm wide Co lines, 24 nm wide Cu with and without a thin Co cap and 24 nm wide Ru lines were tested. These data showed that Cu with a Co cap, Co and Ru had highly reliable EM, although Ru was better than Co and Co was better Cu. The electromigration activation energies for Cu with Co cap and Co were found to be 1.5–1.6 eV and 2.1–2.7 eV, respectively.

Methods to lower the resistivity of ruthenium interconnects at 7 nm node and beyond

36 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Different adhesion layers are used to form the Ru interconnects. Ru line resistivity is measured by the temperature coefficient of resistivity method, and the area verified by TEM. Ru line resistivity is found to depend on the adhesion layer. The adhesion layers with higher intrinsic resistivities reduced the Ru line resistivity. A ∼10% Ru resistivity reduction can be achieved with ALD TaN or TiN adhesion layers or oxidized TaN, relative to PVD TaN. Grain boundary scattering may play an additional role, as demonstrated by different aspect ratio samples. The lowest Ru resistivity in these interconnects is 15 µΩ-cm, at a cross-sectional area of 300 nm2. Ru damascene metallization is extendible to features with critical dimension around 10 nm. Ru may match Cu line resistance for line dimensions below ∼17 nm.