Rajeev Malik
IBM
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Rajeev Malik.
custom integrated circuits conference | 2005
Victor Chan; Ken Rim; Meikei Ieong; Sam Shixiong Yang; Rajeev Malik; Young Way Teh; Min Yang; Qiqing
Device improvement with strain engineering is considered a way to enhance the carrier mobility. Several stress-transfer techniques (such as etch-stop liner, stress transfer technique, e-SiGe) using extra integration process into an existing baseline process is demonstrated. In addition, new preparation techniques of strained-Si surface (e.g. biaxial tensile stress) and different substrate orientation to enhance mobility are introduced. The challenges and vitality of each method are discussed and compared. In addition, we highlight how the stress oriented from the layout geometry affects the device electrical behavior. The issues and improvement in the circuit level device modeling are discussed.
international conference on ic design and technology | 2012
Balaji Jayaraman; Sneha Gupta; Yanli Zhang; Puneet Goyal; Herbert L. Ho; Rishikesh Krishnan; Sunfei Fang; Sungjae Lee; Douglas Daley; Kevin McStay; John E. Barth; Sadanand V. Deshpande; Paul C. Parries; Rajeev Malik; Paul D. Agnello; Scott Richard Stiffler; Subramanian S. Iyer
In this paper, we present a systematic performance study and modeling of on-chip deep trench (DT) decoupling capacitors for high-performance SOI microprocessors. Based on system-level simulations, it is shown that the DT decoupling capacitors (decap) offer significant area advantage over the other two conventional decoupling capacitors - Metal-oxide-semiconductor (MOS) and Metal-Insulator-Metal (MIM). The fabrication process flow of DT decap is borrowed from regular eDRAM process and adds no additional process cost to processors that utilize large eDRAM cache [1]. We demonstrate that, with new process innovations such as introduction of High-k/metal gate and new plate doping methodology, there is significant reduction in equivalent series resistance (ESR) of the trench resulting in ~3.5X improvement in half capacitance frequency for 32nm node. Further, with 22nm technology, improved ESR, DT Decaps performance is significantly enhanced, hence showing that DT-decaps can be reliably used for technology beyond 32nm.
international soi conference | 2010
Geng Wang; C. Radens; J. Safran; C. Pei; G. Freeman; Paul C. Parries; Rajeev Malik; S. S. Iyer
The transition to multicore computing demands more embedded cache memories. Incorporating high performance eDRAMs into the cache hierarchy is an attractive solution. In this paper, we discuss the roles of SRAM, eDRAM and eFUSE OTPROM in a high performance SOI chip.
Archive | 2004
Rama Divakaruni; Thomas W. Dyer; Rajeev Malik; Jack A. Mandelman; Venkatachalam C. Jaiprakash
Archive | 2004
Ramachandra Divakaruni; Oleg Gluschenkov; Oh-Jung Kwon; Rajeev Malik
Archive | 2004
Ramachandra Divakaruni; Oleg Gluschenkov; Oh-Jung Kwon; Rajeev Malik
Archive | 2000
Venkatachalam C. Jaiprakash; Jack A. Mandelman; Ramachandra Divakaruni; Rajeev Malik; Mihel Seitz
Archive | 2003
Wai-kin Li; Rajeev Malik; Joseph Mezzapelle
Archive | 2001
Helmut Tews; Johnathan E. Faltermeir; Rajeev Malik; Carol J. Heenan; Oleg Gluschenkov
Archive | 2003
Rama Divakaruni; Thomas W. Dyer; Rajeev Malik; Jack A. Mandelman; Venkatachajam C. Jaiprakash