Rajeev Malik

Strain for CMOS performance improvement

Device improvement with strain engineering is considered a way to enhance the carrier mobility. Several stress-transfer techniques (such as etch-stop liner, stress transfer technique, e-SiGe) using extra integration process into an existing baseline process is demonstrated. In addition, new preparation techniques of strained-Si surface (e.g. biaxial tensile stress) and different substrate orientation to enhance mobility are introduced. The challenges and vitality of each method are discussed and compared. In addition, we highlight how the stress oriented from the layout geometry affects the device electrical behavior. The issues and improvement in the circuit level device modeling are discussed.

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond

In this paper, we present a systematic performance study and modeling of on-chip deep trench (DT) decoupling capacitors for high-performance SOI microprocessors. Based on system-level simulations, it is shown that the DT decoupling capacitors (decap) offer significant area advantage over the other two conventional decoupling capacitors - Metal-oxide-semiconductor (MOS) and Metal-Insulator-Metal (MIM). The fabrication process flow of DT decap is borrowed from regular eDRAM process and adds no additional process cost to processors that utilize large eDRAM cache [1]. We demonstrate that, with new process innovations such as introduction of High-k/metal gate and new plate doping methodology, there is significant reduction in equivalent series resistance (ESR) of the trench resulting in ~3.5X improvement in half capacitance frequency for 32nm node. Further, with 22nm technology, improved ESR, DT Decaps performance is significantly enhanced, hence showing that DT-decaps can be reliably used for technology beyond 32nm.

Embedded memory considerations in SOI

The transition to multicore computing demands more embedded cache memories. Incorporating high performance eDRAMs into the cache hierarchy is an attractive solution. In this paper, we discuss the roles of SRAM, eDRAM and eFUSE OTPROM in a high performance SOI chip.