Fabian Oboril

ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level

With shrinking feature sizes, transistor aging due to NBTI and HCI becomes a major reliability challenge for microprocessors. These processes lead to increased gate delays, more failures during runtime and eventually reduced operational lifetime. Currently, to ensure correct functionality for a certain operational lifetime, additional timing margins are added to the design. However, this approach implies a significant performance loss and may fail to meet reliability requirements. Therefore, aging-aware microarchitecture design is inevitable. In this paper we present ExtraTime, a novel microarchitectural aging analysis framework, which can be used in early design phases when detailed transistor-level information is not yet available to model, analyze, and predict performance, power and aging. Furthermore, we show a comprehensive investigation using ExtraTime of various clock and power gating strategies as well as aging-aware instruction scheduling policies as a case study to show the impact of the architecture on aging.

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as nonvolatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this paper, we provide a very detailed analysis of SOT-MRAM at both the circuit-and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that a hybrid-combination of SRAM for the L1-Data-cache, SOT-MRAM for the L1-Instruction-cache and L2-cache can reduce the energy consumption by 60% while the performance increases by 1% compared to an SRAM-only configuration. Moreover, the retention failure probability of SOT-MRAM is 27× smaller than the probability of radiation-induced Soft Errors in SRAM, for a 65 nm technology node. All of these advantages together make SOT-MRAM a viable choice for microprocessor caches.

Aging-aware logic synthesis

As CMOS technology scales down into the nanometer regime, designers have to add pessimistic timing margins to the circuit as guardbands to avoid timing violations due to various reliability effects, in particular accelerated transistor aging. Since aging is workload-dependent, the aging rates of different paths are non-uniform, and hence, design time delay-balanced circuits become significantly unbalanced after some operational time. In this paper, an aging-aware logic synthesis approach is proposed to increase circuit lifetime with respect to a specific guardband. Our main objective is to optimize the design timing with respect to post-aging delay in a way that all paths reach the assigned guardband at the same time. In this regard, in an iterative process, after computing the post-aging delays, the lifetime is improved by putting tighter timing constraints on paths with higher aging rate and looser constraints on paths which have less post-aging delay than the desired guarband. The experimental results shows that the proposed approach improves circuit lifetime in average by more than 3X with negligible impact on area. Our approach is implemented on top of a commercial synthesis toolchain, and hence scales very well.

Avoiding unnecessary write operations in STT-MRAM for low power implementation

Spin Transfer Torque (STT) is a promising emerging memory technology because of its various advantages such as non-volatility, high density, virtually infinite endurance, scalability and CMOS compatibility. Despite all these features, high write current is still a challenge for its widespread use. When writing a value that is already stored, a significant current flows through the Magnetic Tunnel Junction (MTJ) cell which is almost the same as that required to flip the stored data. This increases the total power consumption of the memory. To address this issue, we propose a technique which can avoid unnecessary write operations with bit-level granularity. Our technique can save 68.9% of the total write power consumption with a minor area overhead (0.68 %) and only a small timing penalty (1.33 %).

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing

This paper deals with a new MRAM technology whose writing scheme relies on the Spin Orbit Torque (SOT). Compared to Spin Transfer Torque (STT) MRAM, it offers a very fast switching, a quasi-infinite endurance and improves the reliability by solving the issue of “read disturb”, thanks to separate reading and writing paths. These properties allow introducing SOT at all-levels of the memory hierarchy of systems and adressing applications which could not be easily implemented by STT-MRAM. We present this emerging technology and a full design framework, allowing to design and simulate hybrid CMOS/SOT complex circuits at any level of abstraction, from device to system. The results obtained are very promising and show that this technology leads to a reduced power consumption of circuits without notable penalty in terms of performance.

Architectural aspects in design and analysis of SOT-based memories

Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as non-volatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this work, we provide a very detailed analysis of SOT-MRAM at both circuit- and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that with a hybrid-combination of SRAM for the L1-cache and SOT-MRAM for the L2-cache the energy consumption can be reduced by 63 % in average while the performance can be increased by 1 %. In addition, the memory area is 43% lower compared to an SRAM-only configuration.

Read disturb fault detection in STT-MRAM

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has potential to become a universal memory technology because of its various advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. However, read disturb is a major reliability issue in which a read operation can lead to a bitflip, because read and write current share the same path. This major reliability challenge is growing with technology scaling as read to write current ratio decreases. In this paper, we propose a circuit-level technique to detect read disturb by sensing the current during the read operation. Experimental results show that the proposed technique can effectively detect read disturb at the cost of negligible power and area overhead.

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions

Transistor aging due to Negative Bias Temperature Instability (NBTI) is a major reliability challenge for embedded microprocessors at nanoscale. It leads to increasing path delays and eventually more failures during runtime. In this paper, we propose a novel microarchitectural approach combining aging-aware instruction scheduling with specialized functional units to alleviate the impact of NBTI-induced wearout. To achieve this, the instructions are classified depending on their worst-case delay into critical (i.e. the instructions whose delay is close to the cycle boundary) and non-critical instructions (i.e. those instruction with larger timing slack). Each of these classes uses its own (specialized) functional unit(s). By that means it is possible to increase the idle ratio of the units executing the critical instructions, which can be used to extend lifetime by up to 2.3x in average compared to the usually used balanced scheduling policy.

Aging mitigation in memory arrays using self-controlled bit-flipping technique

With CMOS technology downscaling into the nanometer regime, the reliability of SRAM memories is threatened by accelerated transistor aging mechanisms such as Bias Temperature Instability (BTI). BTI leads to a considerable degradation of SRAM cell Static Noise Margin (SNM), which increases the memory failure rate. Since BTI is workload dependent, the aging rates of different cells in a memory array are quite non-uniform. To address this issue, a variety of bit-flipping techniques has been proposed to decrease the SNM degradation by balancing the signal probabilities of the cells. However, existing bit-flipping techniques impose too much area and power overhead as at least an additional column is required to store the inversion flags. In this paper, we propose a low cost self-controlled bit-flipping technique which inverts all bit positions with respect to an existing bit. This technique is applied to a register-file and cache units of an embedded microprocessor. Our simulation results show that the reliability of the proposed technique is similar to that of existing bit-flipping techniques, while imposing 64% less area overhead.

Aging-Aware Design of Microprocessor Instruction Pipelines

As complementary metal-oxide-semiconductor technologies enter nanometer scales, microprocessors become more vulnerable to transistor aging, mainly due to bias temperature instability and hot carrier injection. These phenomena lead to increasing device delays during the operational lifetime, which result in growing delays of the instruction pipeline stages. However, the aging rates of different stages are different. Hence, a previously delay-balanced pipeline becomes increasingly imbalanced resulting in a non-optimized design in terms of lifetime [i.e., mean time to failure (MTTF)], frequency, area, and power consumption. In this paper, we propose an aging-aware, MTTF-balanced pipeline design, in which the pipeline stage delays are balanced at the desired lifetime rather than at design time. This can lead to significant MTTF (lifetime) improvements as well as additional performance, area, and power benefits. Our experimental results show that for two different microprocessors, MTTF can be extended by at least 2.3 times while achieving an additional 10% energy improvement with no penalty on delay and area. If the demand for performance is higher than that for a longer MTTF, it is also possible to improve the clock frequency by 2%.