Mohammad Saber Golanbari

Variation-aware near threshold circuit synthesis

Near-Threshold Computing (NTC) is shown to be a promising approach for improving the energy efficiency of VLSI circuits. Nevertheless, by reducing the supply voltage the delay impact of process variation significantly increases, leading to up to 20× performance variation compared to the nominal voltage. As a result, it is wasteful of energy and performance to deal with such variation by increasing the timing margins, which is common in nominal voltage. Therefore, considering the impact of process variation during the near-threshold circuit design phase is of decisive importance. In this paper, we propose a variation-aware synthesis flow for NTC to address this problem. The objective is to improve the performance and energy efficiency of a circuit during design time by considering statistical variation information. This is done by providing variation information to the synthesis tool, evaluating the performance of the synthesized circuit by Statistical Static Timing Analysis (SSTA), and adjusting the timing constraints accordingly in an iterative manner. Simulation results for a set of benchmark circuits show that our proposed flow reduces the variation by 86.6% and improves the performance and energy by 24.9% and 7.4%, respectively, at the expense of 4.8% area overhead.

Aging guardband reduction through selective flip-flop optimization

Bias Temperature Instability (BTI) affects both timing and functionality of Flip-Flops (FFs). In a typical processor, a considerable portion of FFs always operate under severe BTI stress independent of the running workload. This leads to a serious timing degradation in these FFs, and to avoid timing violations in field, they mandate a large aging guardband (timing margin). In this paper, we propose a method to mitigate the BTI-induced aging of such FFs via transistor sizing optimization. The optimized FFs are more resilient against BTI stress compared to the original ones. The imposed overall leakage is negligible, and the area of the optimized FFs is similar to the original ones in order to facilitate the replacement of the original FFs with optimized alternatives in the circuit layout. Simulation results show that incorporating the optimized FFs in a processor can reduce the timing guardband of the processor by 22.8% compared to the original design, which translates into prolonged lifetime and more reliability.

Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization

Near threshold computing (NTC) has the potential to reduce the energy consumption by orders of magnitude. However, NTC designs suffer from a higher sensitivity to process variation and substantial performance degradation. In NTC, process variation affects the delays of different pipeline stages significantly, resulting in energy-inefficient designs. In this paper, we propose an energy-efficient variation-aware processor pipeline optimization, in which the pipeline stages are balanced by considering the impact of process variation during earlier design phases. This can lead to a well-balanced design and significant improvement in energy-efficiency. For this purpose, we employ an iterative variation-aware synthesis flow in which the synthesis tool is provided with variation information. Since the impact of process variation is considered during synthesis, our technique can improve the energy-efficiency by avoiding pessimistic guard band. Simulation results show that our technique can improve the energy-efficiency of OpenSPARC and FabScalar cores by 55% and 85%, respectively.

A cross-layer approach for resiliency and energy efficiency in near threshold computing

Energy constrained systems become the cornerstone of emerging energy harvested or battery-limited applications in Internet of Thing (IoT) platforms. A promising approach is to operate at near threshold voltage ranges, which can significantly reduce energy per operation. However, due to increased sensitivity to variations and reduced noise margin at low voltages, resiliency becomes a major challenge. In this paper we provide a cross layer approach, from compiler all the way to circuit design, to maximize the energy efficiency as well as the resiliency of functional units. The key idea is to identify the instructions which become timing critical at low voltages and address them by a combination of circuit redesign, multi-cycle execution and code replacement. This allows us to significantly reduce timing failures and at the same time limit leakage energy, which becomes considerable at low voltages. This approach enables resilient and energy efficient operation in a wide voltage range to trade off energy and performance.

Analysis and optimization of flip-flops under process and runtime variations

Process and runtime variations affect the functionality of nanoscale VLSI designs which leads to reduced manufacturing yield and increased runtime failures. In this paper, a comparative analysis of the impact of process and runtime variations on the performance of flip-flops (FF) is carried out. Our analysis shows that independent consideration of the effect of different sources of variations may result in significant inaccuracy compared to the combined effect analysis, and leads to sub-optimal designs. In particular, our analysis reveals that the particular FF designs which are resilient to the process variation are not the best choices for the combined effects of process and runtime variations. Furthermore, we develop a framework to design and optimize resilient FFs against process and runtime variations. The results indicate that the framework is able to reduce the timing failure of FFs up to 99.5%.

Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing

Power and energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultralow power and energy-harvested systems. Aggressive voltage scaling and in particular near-threshold computing is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runtime variation. Temperature variation is one of the major sources of performance variation. In this paper, we study the impact of temperature variation on the circuit behavior in the near-threshold voltage region and show that the ambient temperature has a huge impact on the metrics such as circuit delay, power, and energy consumption. We also propose a low-cost, ambient temperature-aware voltage scaling technique to reduce the unnecessary energy overhead caused by temperature variation. Simulation results show that our proposed approach reduces the energy consumption by more than

Hold-time violation analysis and fixing in near-threshold region

1.95\times

Fault injection acceleration by simultaneous injection of non-interacting faults

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Post-fabrication calibration of Near-Threshold circuits for energy efficiency

Operating in the Near Threshold Voltage (NTV) region improves the energy-efficiency of CMOS circuits by an order of magnitude. However, the number of hold-time violations significantly grows by scaling the supply voltage to the NTV region due to the increased delay variations. Furthermore, the conventional hold-time fixing approaches based on corner analysis are not applicable to the NTV region. In this paper, we propose a new iterative hold-time fixing flow for the NTV region based on Statistical Static Timing Analysis. The experimental results show 43.3% (35.4%) less energy (area) overhead compared to the conventional approach.

VAET-STT: A variation aware estimator tool for STT-MRAM based memories

Fault injection is the de facto standard for evaluating the sensitivity of digital systems to transient errors. Due to various masking effects only a very small portion of the injected faults lead to system-level failures, and hence, too many faults have to be injected for achieving statistically meaningful results. At the same time, since the majority of injected faults will be masked, lots of simulation cycles will be wasted for tracking each and every injected fault separately. In this paper, we propose an opportunistic acceleration technique which evaluates the impact of multiple non-interacting faults in one workload execution. In case no failure is observed, this technique skips the evaluation of those individual faults which leads to a significant speedup. The experimental results on the Leon3 processor show that our proposed technique shortens the fault injection runtime by two orders of magnitude.