Anteneh Gebregiorgis
Karlsruhe Institute of Technology
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Featured researches published by Anteneh Gebregiorgis.
asia and south pacific design automation conference | 2015
Anteneh Gebregiorgis; Mojtaba Ebrahimi; Saman Kiamehr; Fabian Oboril; Said Hamdioui; Mehdi Baradaran Tahoori
With CMOS technology downscaling into the nanometer regime, the reliability of SRAM memories is threatened by accelerated transistor aging mechanisms such as Bias Temperature Instability (BTI). BTI leads to a considerable degradation of SRAM cell Static Noise Margin (SNM), which increases the memory failure rate. Since BTI is workload dependent, the aging rates of different cells in a memory array are quite non-uniform. To address this issue, a variety of bit-flipping techniques has been proposed to decrease the SNM degradation by balancing the signal probabilities of the cells. However, existing bit-flipping techniques impose too much area and power overhead as at least an additional column is required to store the inversion flags. In this paper, we propose a low cost self-controlled bit-flipping technique which inverts all bit positions with respect to an existing bit. This technique is applied to a register-file and cache units of an embedded microprocessor. Our simulation results show that the reliability of the proposed technique is similar to that of existing bit-flipping techniques, while imposing 64% less area overhead.
international symposium on low power electronics and design | 2016
Anteneh Gebregiorgis; Mohammad Saber Golanbari; Saman Kiamehr; Fabian Oboril; Mehdi Baradaran Tahoori
Near threshold computing (NTC) has the potential to reduce the energy consumption by orders of magnitude. However, NTC designs suffer from a higher sensitivity to process variation and substantial performance degradation. In NTC, process variation affects the delays of different pipeline stages significantly, resulting in energy-inefficient designs. In this paper, we propose an energy-efficient variation-aware processor pipeline optimization, in which the pipeline stages are balanced by considering the impact of process variation during earlier design phases. This can lead to a well-balanced design and significant improvement in energy-efficiency. For this purpose, we employ an iterative variation-aware synthesis flow in which the synthesis tool is provided with variation information. Since the impact of process variation is considered during synthesis, our technique can improve the energy-efficiency by avoiding pessimistic guard band. Simulation results show that our technique can improve the energy-efficiency of OpenSPARC and FabScalar cores by 55% and 85%, respectively.
international conference on computer aided design | 2016
Mohammad Saber Golanbari; Anteneh Gebregiorgis; Fabian Oboril; Saman Kiamehr; Mehdi Baradaran Tahoori
Energy constrained systems become the cornerstone of emerging energy harvested or battery-limited applications in Internet of Thing (IoT) platforms. A promising approach is to operate at near threshold voltage ranges, which can significantly reduce energy per operation. However, due to increased sensitivity to variations and reduced noise margin at low voltages, resiliency becomes a major challenge. In this paper we provide a cross layer approach, from compiler all the way to circuit design, to maximize the energy efficiency as well as the resiliency of functional units. The key idea is to identify the instructions which become timing critical at low voltages and address them by a combination of circuit redesign, multi-cycle execution and code replacement. This allows us to significantly reduce timing failures and at the same time limit leakage energy, which becomes considerable at low voltages. This approach enables resilient and energy efficient operation in a wide voltage range to trade off energy and performance.
design, automation, and test in europe | 2016
Anteneh Gebregiorgis; Saman Kiamehr; Fabian Oboril; Rajendra Bishnoi; Mehdi Baradaran Tahoori
Near Threshold Computing (NTC) is a promising approach to reduce the power consumption of modern VLSI designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the most out of NTC. This paper presents a cross-layer reliability analysis in the presence of soft errors, aging and process variation effects in the near threshold voltage domain. The objective is to quantify the reliability of different SRAM designs and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this work, the Soft Error Rate (SER) and Signal Noise Margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit and architecture level analysis. Their experimental results reveal that in NTC, process variation and aging-induced SNM degradation is 2.5X higher than in the super threshold domain while SER is 8X higher. The use of 8T instead of 6T SRAM cells can reduce the system-level SNM and SER by 14% and 22% respectively. Besides, we observe that we can find the right balance between performance and reliability by using an appropriate cache organization at NTC which is different from the super threshold.
international symposium on quality electronic design | 2017
Mohammad Saber Golanbari; Saman Kiamehr; Fabian Oboril; Anteneh Gebregiorgis; Mehdi Baradaran Tahoori
Scaling supply voltage to the Near-Threshold Voltage (NTV) region is an effective approach for energy-constrained circuit design at the cost of performance reduction. However, the impacts of process and runtime variations on the circuits operating at NTV aggravate due to the larger sensitivity to variations. This sensitivity changes the performance and power consumption of the circuit impacting the Minimum Energy Point (MEP). Therefore, finding an optimum operating voltage for Near-Threshold Computing (NTC) in a per-chip basis to account for variability is very challenging. In this paper, we propose a post-fabrication calibration approach based on machine learning in which the optimal supply voltage of each chip is determined during manufacturing test according to basic characteristics of the circuits such as dynamic and leakage power. Unlike the conventional approaches which find the MEP during runtime, the proposed technique imposes almost no overhead (area and power) to the circuit. The simulation results show a significant improvement (59.1%) in the energy efficiency compared to the state-of-the-art approaches.
IEEE Transactions on Very Large Scale Integration Systems | 2018
Anteneh Gebregiorgis; Mehdi Baradaran Tahoori
Energy-constrained microprocessor design plays an important role in many emerging Internet of Things platforms operating on harvested or limited energy budget. For this purpose, operating at the supply voltage corresponding to the minimum energy point (MEP) can achieve significant energy savings. However, the MEP voltage is highly dependent on the threshold voltage, the structure, and the activity rate of the circuit. This is more pronounced in pipelined processors as different pipeline stages have different structure with huge intrinsic activity rate variations. Therefore, the energy-saving is limited when only a single MEP voltage is chosen for the entire microprocessor. To address this issue, we propose a fine-grained MEP tuning technique, in which the individual pipeline stages are designed to operate at their MEPs, through per pipeline stage supply and threshold voltage tuning, by considering their activity rates. The proposed optimization is applied to two processors, FabScalar and OpenSPARC, and simulation results show that the proposed technique can improve the energy efficiency of both the cores by almost 50%. The improvement in energy efficiency is obtained at the cost of 6% performance and < 2% area overhead.
design automation conference | 2017
Anteneh Gebregiorgis; Saman Kiamehr; Mehdi Baradaran Tahoori
Near threshold computing (NTC) through aggressive supply voltage scaling has the potential to significantly improve energy-efficiency. However, the increase in variation-induced timing errors is a major challenge in NTC. This can be addressed in the scope of approximate computing by selectively embracing non-important variation-induced timing errors. In this paper, we propose a framework to leverage the error tolerance potential of approximate computing for energy-efficient NTC designs. In our framework, statistical timing error analysis as well as structural and functional error propagation analysis is performed to identify the approximable portion of a design. Then, a mixed-timing logic synthesis is employed to improve energy-efficiency by embracing errors in the approximable portion of the design. Experimental results show that the proposed approach can improve the energy-efficiency of NTC designs by more than 30%.
2017 International Mixed Signals Testing Workshop (IMSTW) | 2017
Anteneh Gebregiorgis; Mehdi Baradaran Tahoori
Energy reduction has become an important issue in the design of battery-powered devices for Internet of Things (IoT) applications. In this regard, lowering the supply voltage close to transistor threshold voltage, commonly known as Near Threshold Computing (NTC), has been a widely used approach to reduce the energy consumption of various designs. However, the energy-saving potential of NTC is hindered by various factors such as variation-induced functional failures of caches. To address this issue and get utmost NTC benefits, we provide a comprehensive analysis of memory failure mechanisms and propose proper mitigation scheme for near threshold caches. In this work, aging and variation-induced memory failures are analyzed first by incorporating device and circuit level models. Afterwards, we employ Built-in Self- Test (BIST) to identify the lowest voltage limit at which each memory block can properly operate. Then, a mitigation scheme is developed by disabling unreliable portion of the cache and mapping their accesses to the reliable portion. Our evaluation using 16KByte cache shows the proposed mitigation scheme can effectively address permanent and transient memory failures and achieve more than 30% energy-saving of near threshold caches with less than 10% reduction in effective cache size and almost negligible increase in cache miss rate.
international symposium on quality electronic design | 2016
Anteneh Gebregiorgis; Fabian Oboril; Mehdi Baradaran Tahoori; Said Hamdioui
The reliability of embedded processors fabricated using nanoscale technology nodes is threatened by accelerated transistor aging particularly, Bias Temperature Instability (BTI). In embedded memories such as instruction caches, BTI degrades the Static Noise Margin (SNM) of the memory cell, which in turn affects the stability of the stored value. Various bit flipping based solutions have been proposed to address BTI-induced aging of memory components. Nevertheless, the state-of-the-art techniques have considerable area and power overheads. In this paper, we propose an aging-aware instruction encoding technique to mitigate BTI-induced aging of instruction caches. Opcode, register and function code fields of an instruction are re-encoded so that the BTI-induced aging of the instruction cache is minimized. Simulation results show that the proposed technique achieves up to 40% SNM degradation improvement (equivalent to 47% MTTF improvement) with a negligible power overhead (0.1%).
Archive | 2014
Anteneh Gebregiorgis