Rajesh Rengarajan

Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN/sub x/) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN/sub x/ for the NFET and ALD-WN/sub x/ for the PFET. Much enhanced drive current (I/sub d/) and transconductance (G/sub m/) values, and reduced off current (I/sub off/) characteristics were attained with ALD-MN/sub x/ gated devices over control poly-Si and PVD-MN/sub x/ devices within controllable V/sub t/ shifts. Excellent scalability of dual work function MN/sub x//high-k gate stack was demonstrated: the EOT was down to 6.6/spl Aring/ with low leakage in a low thermal budget device scheme.

Array pass transistor design in trench cell for Gbit DRAM and beyond

Aggressive scaling of the DRAM cell size requires minimum dimensions in both the channel length and the channel width of the array pass transistor. As a result of the stringent leakage current requirement, the design for the array MOSFET becomes increasingly challenging as cell size is reduced. In this paper, we present data that illustrate the importance of the channel and the source/drain engineering, along with considerations of minimizing the junction leakage. By utilizing a 512 k array diagnostic monitor, a methodology is presented for optimum array cell design in a statistically reliable manner. Design issues unique to the trench capacitor cell are covered. Alternative biasing schemes that boost the process window are also discussed.

Nitrogen-induced transient enhanced diffusion of dopants

Studies of both systematic experiments and detailed simulations for examining the effects of N2+ implant on channel dopants are described. Step-by-step monitor wafer experiments have clearly confirmed the nitrogen-induced transient enhanced diffusion (TED) of dopants. Process simulations within the “+1” N2+ profile approach have demonstrated the need to scale down the +1 model parameter for matching the measured depth profiles. The underlying mechanism for the reduced +1 model parameter is that nitrogen which diffuses toward the Si surface becomes a sink for the interstitials. These combined studies also show that nitrogen-induced TED of dopants increases with N2+ dose.

Threshold voltage roll-up/roll-off characteristic control in sub-0.2-/spl mu/m single workfunction gate CMOS for high-performance DRAM applications

Threshold voltage (V/sub t/) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-/spl mu/m single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N/sub 2/ implant prior to gate oxidation is important to reduce V/sub t/ roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V/sub t/ roll-off characteristics. Finally, the impact of halo implant on V/sub t/ variation in sub-0.2-/spl mu/m buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V/sub t/ variation in sub-0.2-/spl mu/m single workfunction gate pFET.

Shallow n/sup +//p/sup +/ junction formation using plasma immersion ion implantation for CMOS technology

We present CMOS transistors with n/sup +//p/sup +/ source/drain extensions doped by AsH/sub 3/ and BF/sub 3/ plasma immersion ion implantation (PIII) for the first time. We successfully demonstrate n/sup +//p/sup +/ shallow junctions with R/sub s/<1 k/spl Omega//sq for CMOS devices. No degradation in gate oxide integrity is observed for either AsH/sub 3/ or BF/sub 3/ PIII. Compared to conventional ion implantation, PIII provides much better short-channel effects and approximately 50% I/sub off/ reduction for both nMOS and pMOS devices. In particular, the flat threshold voltage roll-off and good performance in buried-channel pMOS devices is the best-reported PIII data to date.

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.

Simultaneous optimization of short-channel effects and junction capacitance in pMOSFET using large-angle-tilt-implantation of nitrogen (LATIN)

A widely used halo implant process of counter doping has a tradeoff between the short channel effects and the parasitic junction capacitance. In this letter, we propose a novel drain engineering concept, large-angle-tilt-implantation of nitrogen (LATIN) to improve the short-channel effects without the increase of the junction capacitance in the buried-channel pMOSFET using sub-0.25-/spl mu/m CMOS technology. We compare the electrical characteristics of devices fabricated using LATIN, a conventional arsenic halo implant process (As HALO), and BF/sub 2//sup +/ source/drain (S/D) implantation only. The LATIN improves the short-channel effects when compared to the case of BF/sub 2//sup +/ S/D implant only. In addition, the LATIN reduces junction capacitance by 18% when compared to As HALO. As a consequence, the LATIN is shown to be a drain engineering concept to simultaneously optimize the short-channel effects and junction capacitance. Calibrated two-dimensional simulations confirm the improvement with LATIN.

Integration of high performance dual workfunction logic CMOS transistors with a dense 8F/sup 2/ vertical DRAM cell

In this paper, we report on integration of high performance dual workfunction logic CMOS transistors with a commodity 8F/sup 2/ vertical DRAM cell for high performance stand-alone DRAM and low-cost low-power embedded DRAM applications. Key process integration features that exploit novel aspects of the vertical DRAM cell to enable a high performance embedded DRAM technology are presented. The impact of pre-metal-dielectric reflow thermal budget on dual workfunction CMOS device characteristics is discussed.

Threshold-voltage anomaly in sub-0.2 /spl mu/m DRAM buried-channel pFET devices

Measurements and simulation have been used to study threshold-voltage (V/sub t/) dependence on gate oxide thickness (t/sub ox/) for long-channel buried-channel (BC-) pFET devices in sub-0.2 /spl mu/m CMOS technologies. The combination of the dual gate oxide process using N/sub 2/ implantation to create the thinner gate oxide and well RTA results in the thinner t/sub ox/ devices having higher V/sub t/, contrary to expectation (V/sub t/-t/sub ox/ anomaly). Detailed analysis of doping profiles, depletion contours, and electric potential confirms this anomaly both in the enhancement and depletion modes of operation. These studies show that a balance of net doping between that near the surface and that around the BC-layer is a stringent requirement for the Vt control in BC-pFETS.