Ramsin M. Ziazadeh

A multistage amplifier technique with embedded frequency compensation

A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-/spl mu/m n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V//spl mu/s average slew rate with 40 pF load.

A multistage amplifier topology with embedded tracking compensation

A new multistage operational amplifier topology requires only n-2 embedded compensation networks for n gain stages. The passive compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power tracking RC compensation technique assures stability and fast settling over process, voltage, and temperature (PVT) variations. In 0.6 /spl mu/m n-well CMOS with 5 pF loads, a single-ended 3-stage prototype dissipates 4.2 mW at 3.0 V with 82 dB gain, 230 MHz bandwidth, and 150 V//spl mu/s slew rate, and a fully-differential 3-stage design dissipates 11 mW at 2.5 V with 122 dB gain, 138 MHz bandwidth, and 360 V//spl mu/s slew rate.