Donald C. Wheeler

Optical lens specifications from the user's perspective

We develop three main topics in support of further understanding and specifying wavefront aberrations from the lithographers point of view. The concept of the Magnitude Weighted Aberration is introduced providing a convenient and rapid numerical method for assessing the interaction of wavefront aberrations with reticle pattern and illumination mode. This analysis suggests that the advanced lithographic lens user will require unprecedented correction on the total wavefront aberration to realize the full potential of the imaging system in high yielding integrated circuit fabrication. Specific details on the required aberration control are provided with a Monte Carlo tolerancing analysis of the RMS wavefront error using lithographic CD control and pattern placement as quality metrics. Patten placement proves to be as sensitive to wavefront aberrations as CD control forcing a tight specification on the asymmetric aberration components even when a large focus and exposure latitude is available. Based on the wavefront specifications generated it is imperative that the lithographic lens user be able to independently de-couple and quantify the state of certain aberration coefficients. Toward this goal, we demonstrate an aberration reverse engineering procedure using experimental pattern placement error as the input response.

Method to budget and optimize total device overlay

We combine lithographic simulation, experimental data and statistical modeling to build a predictive estimator of total device overlay. To generate accurate predictions of total overlay, we include error estimates on lens image placement, CD control, reticle and exposure tool alignment. Instead of combining these errors in ad hoc root sum square fashion to make overlay estimates, we construct a physical model of the device and metrology marker edge placement processes. The model comprehends the differential placement of metrology structures and device features due to lens and illumination system asymmetries and is therefore applicable to the evaluation of arbitrary illumination and pattern geometry conditions. Since we attempt to model the relative placement distribution of specific device features, the model produces overlay estimates that are directly relevant for device performance. The comparison of our total overlay estimate to device overlay sensitivity data allows a projection of the overlay related yield loss for a given device, process and tools et. Finally, our model allows the process engineer to made informative choices on the optimum error sources to pursue for improving overlay.

Phase-shift focus monitor applications to lithography tool control

Through the use of phase shift techniques, focus errors have been demonstrated to result in easily measurable overlay shifts in printed resist patterns. Using box-in-box with phase shifter design, patterns are printed on wafers and measured on standard overlay equipment. Results are compared to more conventional methods of focus detection. Details include measurement and calibration methodology, focus, and focus tilt results. Additionally, SPC in IBMs ASTC Fab is demonstrated with the Phase Shift Focus Monitor.

Subwavelength alignment mark signal analysis of advanced memory products

The impact of alignment mark structure, mark geometry, and stepper alignment optical system on mark signal contrast was investigated using computer simulation. Several sub-wavelength poly silicon recessed film stack alignment targets of advanced memory products were studied. Stimulated alignment mark signals for both dark-field and bright-field systems using the rigorous electromagnetic simulation program TEMPEST showed excellent agreement with experimental data. For a dark-field alignment system, the critical parameters affecting signal contrast were found to be mark size and mark recess depth below silicon surface. On the other hand, film stack thickness and mark recess depth below/above silicon surface are the important parameters for a bright-field alignment system. From observed simulation results optimal process parameters are determined. Based on the simulation results some signal enhancement techniques will be discussed.

Challenge of 1-Gb DRAM development when using optical lithography

The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.

Characterization of a next-generation step-and-scan system

Deep-ultaviolet (DUV) step-and-scan projection systems have been increasing in semiconductor manufacturing importance in recent years. IBM and other semiconductor manufacturers have made substantial use of 0.50 numerical aperture (NA) step-and- scan systems for production resolutions down to approximately 250 nm resolution. This paper describes the initial system characterization and product performance of a next generation, 0.60 NA scanner system in early semiconductor production.

A multilayered ceramic (MLC) interface design for 125+MHz performance wafer probing (of SRAMs)

A design is presented using a multilayered ceramic (MLC) substrate as the basis for the wafer-tester interface. A 27*27 matrix of pads on 225 mu m centers is contacted; this design replaces a hand-wire interface between the wafer probe and tester performance board. Significant reductions in signal crosstalk and power supply noise are realized.<<ETX>>