Renaud Ambroise

Interests and Limitations of Technology Scaling for Subthreshold Logic

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.

Analysis and minimization of practical energy in 45nm subthreshold logic circuits

Over the last decade, the design of ultra-low-power digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contribution, we observe that operating at minimum-energy point is not straightforward as design constraints from real-life applications have an important impact on energy. Therefore, we introduce the alternative concept of practical energy, taking functional-yield and throughput constraints on minimum Vdd into account. In this context, we demonstrate for the first time the detrimental impact of DIBL on minimum Vdd. Practical energy gives a useful analysis framework of circuit optimization to reach minimum-energy point, while considering the throughput as an input variable dictated by the application. From simulation of a benchmark multiplier in 45 nm technology, we find out that practical energy can be far higher than minimum energy point, in the case of low-throughput applications (ap 10-100 kOp/s) because of static leakage energy and robustness-limited minimum Vdd. With the proposed framework, we investigate the capability of conventional optimization techniques to make practical energy meet minimum energy point. Amongst these techniques, channel length upsize is shown to be more efficient than MTCMOS power gating, body biasing, Vt selection or device width upsize, as it increases robustness while simultaneously reducing static leakage energy. A small length upsize with low area overhead is shown to reduce practical energy at low throughput to less than 2.1 times the minimum energy level. At medium throughput, it even brings practical energy 30% lower than minimum energy level without optimization techniques.

Sub-45nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications

The improved immunity of FD SOI technology against short-channel effects has been shown to offer a great interest for subthreshold logic in terms of delay and energy per operation at medium throughputs (108 Op/s). Moreover, the combination of an undoped channel with a metal gate extends this benefit to lower throughputs by a reduction of the minimum functional Vdd and static energy. This makes FD SOI with metal gate a strong candidate for sub-45 nm robust and energy-efficient subthreshold circuits.

Impact of Technology Scaling on Digital Subthreshold Circuits

Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circuits is investigated. Migrating from 0.25-mum to 32-nm node is shown to considerably lower the energy consumption of a subthreshold 8x8-bit RCA multiplier. When reaching the smallest nodes, limitations come from slow scaling of the static energy consumption and the deteriorating static noise margin, which raises robustness issues when considering process variability. These effects result in a loss of energy efficiency. The use of non-minimum channel length is proposed to improve energy efficiency. At 32-nm node, it reduces total energy consumption by a factor 5.

Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards

This paper proposes different low-cost coprocessors for public key authentication on 8-bit smart cards. Elliptic curve cryptography is used for its efficiency per bit of key and the Elliptic Curve Digital Signature Algorithm is chosen. For this functionality, an area constrained coprocessor is probably the best approach to perform the most computer-intensive operations at an acceptable speed considering the limited memory and power of the selected platform. For that purpose, the scalar point multiplication in GF(2m) in both affine and projective coordinates was implemented in order to compare their performances with the same level of optimization and the same technology. A hardware/ software co-design strategy was also used to avoid the need of a dedicated register file.

Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices

Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for ultra-low-power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-VGS self-biasing ULP logic gates have static current reduced by several orders of magnitude. For a commercial 0.13-mum technology, power consumption of ULP gates at low frequencies is lower than standard CMOS counterparts even considering high-VT devices, subthreshold operation and reverse body biasing. ULP gates are shown to be very stable against process, voltage and temperature variations.

Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications

In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural levels, by using extensive clock and data gating, and by completely redesigning the micro-architecture. We also present original clock gating techniques: pre-computed clock gating. To validate these techniques, simulation results are compared with other realizations of the same microcontroller. It shows that gating techniques can achieve good performances. All comparison results are then validated by measures achieved on a chip prototype.

Low power techniques applied to a 80c51 microcontroller for high temperature applications

In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and data gating, and by completely redesigning the micro-architecture. We also present original clock gating techniques: pre-computed clock gating. To validate these techniques, extensive comparisons with other realizations of the same microcontroller are presented. It shows that gating techniques can achieve good performances.