Richard Schenker

Pixelated Phase Mask as Novel Lithography RET

Novel RET-Pixelated Phase Mask (PPM) is proposed as a novel Resolution Enhancement Technique (RET). PPM is made of pixels of various phases with lateral dimensions significantly smaller than the illuminating radiation wavelength. Such PPM with a singular choice of pixel dimensions acts as a mask with variable phase and transmission due to radiation scattering and attenuation on pixel features with the effective intensity and phase modulated by the pixel layout. Key properties of the pixelated phase masks, the steps for their practical realization, and the benefits to random logic products discussed. Wafer patterning performance and comparative functional yield results obtained for a 65nm node microprocessor patterned with PPM, as well as current PPM limitations are also presented.

Lithography strategy for 65-nm node

Intel will start high volume manufacturing (HVM) of the 65nm node in 2005. Microprocessor density and performance trends will continue to follow Moores law and cost-effective patterning solutions capable of supporting it have to be found, demonstrated and developed during 2002-2004. Given the uncertainty regarding the readiness and respective capabilities of 157nm and 193nm lithography to support 65nm technology requirements, Intel is developing both lithographic options and corresponding infrastructure with the intent to use both options in manufacturing. Development and use of dual lithographic options for a given technology node in manufacturing is not a new paradigm for Intel: whenever introduction of a new exposure wavelength presented excessive risk to the manufacturing schedule, Intel developed parallel patterning approaches in time for the manufacturing ramp. Both I-line and 248nm patterning solutions were developed and successfully used in manufacturing of the 350nm node at Intel. Similarly, 248nm and 193nm patterning solutions were fully developed for 130nm node high volume manufacturing.

Patterning challenges in the fabrication of 12 nm half-pitch dual damascene copper ultra low-k interconnects

Earlier [1, 2] work highlighted an integrated process for electrically functional 12 nm half-pitch copper interconnects in an ultralow-k interlayer dielectric (ILD). In this paper, we focus on understanding and reducing undesired effects such as pattern asymmetry/distortion, and line undulation/ collapse. Key defect modes and possible solution paths are discussed. Line undulation can occur when the ILD feature changes shape under the stress of the sacrificial hard mask(s) (HM) during patterning, resulting in “wavy” instead of straight features. The amount of undulation is directly related to mechanical properties such as elastic modulus, residual stresses of patterned HMs and the ILD, as well as the dimensions and aspect ratio of the features. Line collapse is observed post wet-clean processing when one or more of the following is true - Insufficient ILD mechanical strength, excessive pattern aspect ratio, or non-uniform drying. Pattern asymmetry, or unequal critical dimensions (CD) of trenches defined by the same backbone, is a typical problem encountered during spacer-based pitch division. In pitch quartering (P/4), three different trench widths result from small variations in backbone lithography, spacer CD and etch bias. Symmetric patterning can be achieved through rigorous control of patterning processes like backbone definition, spacer deposition and downstream etches. Plasma-based ash and energetic metal deposition were also observed to degrade patterning fidelity of ultra low-k film, and also need to be closely managed.

Integration of pixelated phase masks for full-chip random logic layers

This work describes the advantages, tolerances and integration issues of using Pixelated Phase Masks for patterning logic interconnect layers. Pixelated Phase Masks (PPMs) can act as variable high-transmission attenuated phase shift masks where the pixelated phase configuration simultaneously optimizes OPC and SRAF generation. Thick mask effects help enable PPMs by allowing larger minimum pixel sizes and phase designs with near equal sized zero and piphase regions. PPMs with a 3-tone pixel mask (un-etched glass, etched glass, chrome) offer more flexible patterning capability compared to 2-tone pixel mask (no chrome) style but at the detriment of a more complex mask making process. We describe the issues and opportunities associated with using PPMs for patterning a 65nm generation first level metal layer of a micro-processor.

The MEEF NILS divergence for low k1 lithography

For tight pitch patterning with sub-wavelength mask features, simulations and wafer data show that many mask stacks that provide superior image contrast, can provide inferior MEEF performance. For example, 6% MoSi EPSM is found to have higher MEEF than binary masks despite having better contrast and exposure latitude when equal lines and spaces on the mask are used to pattern equal lines and spaces on the wafer. Likewise, the deposition of SiO2 on-top of the chrome surface of a binary mask improves contrast but degrades MEEF compared to a binary mask. When contrast is varied by mask stack or by print bias, MEEF is poorly correlated with contrast and often increases with increasing contrast. The optimal print bias for exposure latitude is significantly different than the optimum print bias for MEEF. MEEF, on the other hand, is highly correlated with the difference between maximum and minimum intensity when one varies mask stack, print bias and illumination. Analytical MEEF equations are derived that support this strong relationship between MEEF and the difference between maximum and minimum intensity.

The role of strong phase shift masks in Intel's DFM infrastructure development

Intel has reported on three separate styles and applications of strong phase shift masks (PSMs) over the last decade including alt-PSM for gate patterning, alt-PSM with assist features for contact patterning and Pixelated Phase Masks (PPMs) for metal layer patterning. Each had a prominent role in Intels Design For Manufacturing (DFM) infrastructure development in terms of design rules and DFM tooling. By gradually inserting design rule changes for alt-PSM for gate patterning starting from the 130nm technology node, density and design impact were minimally effected. Alt-PSM for contact layer required development of complex methods of SRAF placement and coloring while also forcing advances in phase shift mask manufacturing infrastructure. Pixelated phase masks for metal patterning when combined with Inverse Lithography Techniques (ILTs) were successful in supporting a high level of flexibility for metal design rules including multiple feature sizes, pitches and two-dimension content.

Fabrication of defect-free full-field pixelated phase mask

Pixelated phase masks rendered from computational lithography techniques demand one generation-ahead mask technology development. In this paper, we reveal the accomplishment of fabricating Cr-less, full field, defect-free pixilated phase masks, including integration of tapeout, front-end patterning and backend defect inspection, repair, disposition and clean. This work was part of a comprehensive program within Intel which demonstrated microprocessor device yield. To pattern mask pixels with lateral sizes <100nm and vertical depth of 170nm, tapeout data management, ebeam write time management, aggressive pattern resolution scaling, etch improvement, new tool insertion and process integration were co-optimized to ensure good linearity of lateral, vertical dimensions and sidewall angle of glass pixels of arbitrary pixelated layout, including singlets, doublets, triplets, touch-corners and larger scale features of structural tones including pit/trench and pillar/mesa. The final residual systematic mask patterning imperfections were corrected and integrated upstream in the optical model and design layout. The volume of 100nm phase pixels on a full field reticle is on the order tera-scale magnitude. Multiple breakthroughs in backend mask technology were required to achieve a defect free full field mask. Specifically, integration of aerial image-based defect inspection, 3D optical model-based high resolution ebeam repair and disposition were introduced. Significant reduction of pixel mask specific defect modes, such as electro static discharge and glass pattern collapse, were executed to drive defect level down to single digit before attempt of repair. The defect printability and repair yield were verified downstream through silicon wafer print test to validate defect free mask performance.

Alternating phase-shift masks for contact patterning

The use of alternating phase shift masks (Alt-PSMs) for poly gate patterning is becoming a well-established method for reducing gate critical dimension (CD) and variability. The application of alt-PSM for other device layers and for improving resolution (minimum pitch) is less developed due to more complex layouts, more stringent mask constraints and cost of ownership restrictions. Resolution of contact pairs and nested contacts is found to be improved using alt-PSM compared to embedded PSMs (EPSMs). To improve the process window of semi-nested and isolated contacts, sub-resolution phase-shifted assist features are employed on the mask. Square assist features, rather than rectangular assist features, are used to reduce mask fabrication requirements as one can use a larger minimum assist feature dimension. Because of high mask error enhancement factors (MEEFs), assist features with dimensions as large as 75% of the nominal contact size can be used without patterning on the wafer. Compared to using alt-PSM for poly gate patterning the use of alt-PSM for tight pitch patterning places additional constraints on mask manufacturing. The smaller phase regions intrinsic to tight pitch patterning result in tighter phase uniformity and mask defect requirements.

Foundations for scaling beyond 14nm

The path to extending Moores Law beyond 14nm technology node will require a combination of advanced imaging, computation, patterning and design methods. Use of phase shift masks in combination with inverse lithography methods can enable imaging of complex, tight pitch patterns. Customizing designs to have asymmetric minimum metal pitch design rules can improve overall density. Pitch division methods like pitch quartering permit scaling beyond physical imaging limits from a single exposure. For example, metal test structures at 24nm pitch are generated using spacer based pitch quartering. Co-optimizing design and process allow application of pitch division to logic devices. Pitch division and Computation Lithography methods can be combined with EUV (Extreme Ultraviolet) lithography to further enhance scaling and design rule flexibility.

Alt-PSM for 0.10-μm and 0.13-μm polypatterning

While the use of phase shift masks can improve CD control and allow the patterning of smaller poly gate features, it also introduces new error terms for overlay. Four error terms are discussed: increased sensitivity of image placement to coma-type aberrations, image placement shifts resulting form phase errors, image placement shifts resulting from intensity imbalance between zero and 180 degrees shifter regions, and phase shift mask to trim mask overlay issues. These overlay issues become increasingly important for lower k1 patterning. Likewise, phase defect printability is magnified for lower k1 patterning, increasing the requirements for phase shift mask inspection and repair.