Richard W. Berger

The RAD750/sup TM/-a radiation hardened PowerPC/sup TM/ processor for high performance spaceborne applications

BAE SYSTEMS has developed the RAD750/sup TM/, a fully licensed radiation hardened implementation of the PowerPC 750/sup TM/ microprocessor, based on the original design database. The processor is implemented in a 2.5 volt, 0.25 micron, six-layer metal CMOS technology. Employing a superscalar RISC architecture, processor performance of 240 million Dhrystone 2.1 instructions per second (MIPS) at 133 MHz is provided, while dissipating less than six watts of power. The RAD750 achieves radiation hardness of 1E-11 upsets/bit-day and is designed for use in high performance spaceborne applications. A new companion ASIC, the Power PCI, provides the bridge between the RAD750, the 33 MHz PCI backplane bus, and system memory. The Power PCI is implemented in a 3.3 volt, 0.5 micron, five-layer metal CMOS technology, and achieves radiation hardness of <1E-10 upsets/bit-day. This paper describes the implementation of both designs.

A new approach to designing electronic systems for operation in extreme environments: Part II - The SiGe remote electronics unit

We have presented the architecture, simulation, packaging, and over-temperature and radiation testing of a complex, 16-channel, extreme environment capable, SiGe Remote Electronics Unit containing the Remote Sensor Interface ASIC that can serve a wide variety of space-relevant needs as designed. These include future missions to the Moon and Mars, with the additional potential to operate in other hostile environments, including lunar craters and around the Jovian moon, Europa. We have expanded on the previous introduction of the RSI to show the validity of the chip design and performance over an almost 250 K temperature range, down to 100 K, under 100 krad TID radiation exposure, with SEL immunity and operability in a high-flux SET environment.

A new approach to designing electronic systems for operation in extreme environments: Part I - The SiGe Remote Sensor Interface

We have described the modeling, circuit design, system integration, and measurement of a Remote Sensor Interface (Figure 20) that took place over a span of 5 years and 8 fabrication cycles. It was conceived as part of the Multi-Chip Module (MCM) shown in Figure 21, which also includes a digital control chip for clocking, programming, and read-out. Further work beyond the scope of this was performed to validate the RSI for the extreme environmental conditions of a lunar mission, and individual blocks are presently.

Applying a high performance tiled rad-hard digital signal processor to spaceborne applications

This paper discusses the architecture and reviews the development of the RADSPEED™ DSP. It illustrates planned board solutions and briefly highlights the other critical components needed such as regulators, bridges to the rest of the spacecraft and high performance memory. The paper describes the various algorithm elements that may apply to the application classes and compiles information on RADSPEED algorithm elements. Lessons learned from development and translation of algorithms from single string to multi-processing elements using the supporting tools are given. For the many spaceborne processing applications that fit onto this architecture, the RADSPEED DSP provides a very high performance / power solution that will scale with the needs of the application.

A SiGe BiCMOS instrumentation channel for extreme environment applications

A instrumentation channel has been designed, implemented and tested in a 0.5-mum SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces a range of external sensors to signal processing circuits. Also, analog sampling has been implemented in the channel using a flying capacitor configuration. Measurement results show the instrumentation channel supports input signals up to 200 Hz.

Reconfigurable and Processing Building Blocks in Responsive Space

[Abstract] Successful responsive spacecraft will likely span a large size range from nanosats on up. If responsive space efforts to standardize, streamline and simplify spacecraft design, integration and launch are successful these efforts will be applied across a variety of processing systems that must be scalable and flexible within the responsive space frameworks. Processing systems in responsive space will require plug and play capability and levels of reconfigurable processing to support this as well as to provide a flexible processing fabric after launch. To provide for reconfigurable signal processing in spacecraft environment, BAE Systems is developing a Universal Field Programmable Gate Array (FPGA) Support Device (UFSD) and demonstrating it on a board to enable responsive space bus and payload instruments to demonstrate modular spacecraft bus standards and interfaces with rapid, low-cost space assets. In parallel, BAE Systems is developing a RAD6000-based integrated microcontroller that can be provide flexible scalable general purpose processing for instruments, controls and data handling for small to medium C&DH and payload units as well as a plug and play port on electronics requiring more than a low speed serial link to interact with other spacecraft assets. This paper will describe the UFSD and RAD6000MC microcontroller architectures and how they, supplemented by other processing elements, may be applied to Plug and Play and other Responsive Space approaches. Taken together we will show how these provide building blocks that will contribute toward the reality of the six to seven day responsive spacecraft.

On-board networks with radiation-hardened 45nm SOI standard components

This paper describes the key components for implementing a modern network for intra-satellite communications at the backplane and spacecraft local area network (LAN) levels. The objective network is capable of supporting orders of magnitude more on-board processing than current architectures based on parallel PCI-bus, MIL-STD-1553B and SpaceWire alone. The RADNET™ family supports the emerging SpaceVPX standard at the backplane level including RapidIO data plane, SpaceWire control plane, and I2C utility plane. RapidIO, SpaceWire and MIL-STD- 1553B are the primary interfaces supported at the spacecraft local area network (LAN) level. Heritage network components are available to support parallel PCI-bus, SpaceWire and MIL-STD-1553B. The latest RADNET components use BAE Systems RH45™ radiation-hardened by design (RHBD) 45nm silicon-on-insulator (SOI) ASIC library and are manufactured at the IBM Trusted foundry. These include a RapidIO network endpoint, an 18-port, 192-Gb/s RapidIO packet switch, and a 16-by-16-lane, 5-Gbaud per lane physical layer serializer-deserializer (SerDes) crosspoint switch. Network architecture, technical challenges, component architectures, development methodology, implementation, programming and path to flight are discussed.

Quad-core radiation-hardened system-on-chip power architecture processor

Based on the QorIQ® system-on-chip processor architecture from Freescale Semiconductor with additional unique features for space applications, the RAD55xxTM system-on-chip platform integrated circuit can be personalized into multiple processor solutions. The RAD55xx platform includes four 32/64 bit Power Architecture® processor cores, three levels of on-die cache memory, dual interleaved DDR3 DRAM controllers, data path acceleration architecture (DPAA) on-die hardware accelerators, a NAND Flash controller, and high I/O throughput based on serializer/deserializer high speed links. Manufactured at the IBM trusted foundry in 45nm silicon-on-insulator (SOI) process technology with copper interconnect and leveraging the radiation-hardened by design RH45TM technology, the RAD55xx platform optimizes power/performance to deliver processor throughput of up to 5.6 GOPS/3.7 GFLOPS, memory bandwidth of up to 102 Gb/s, and I/O throughput of up to 64 Gb/s. Each of the highly efficient RAD5500™ 64-bit cores offers direct addressability to 64 GB of memory, improves double precision floating point performance, and achieves 3.0 Dhrystone MIPS/MHz. The RAD55xx platform is designed for insertion into systems using the SpaceVPX standard, supporting the RapidIO data plane, SpaceWire control plane, and I2C utility plane. Architectural trades, the development methodology, technical challenges, and single board computer solutions are discussed.

A sige BiCMOS instrumentation channel for extreme environment applications

A instrumentation channel has been designed, implemented and tested in a 0.5-mum SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces a range of external sensors to signal processing circuits. Also, analog sampling has been implemented in the channel using a flying capacitor configuration. Measurement results show the instrumentation channel supports input signals up to 200 Hz.

Event driven mixed signal modeling techniques for System-in-Package functional verification

Developing complex mixed-signal System-in-Package (SiP) chip-sets or Systems-on-Chip (SoC) typically involves parallel analog and digital IC development, where verification engineers can expect to encounter disconnects between the design automation flows, user proficiencies, and IC release cycles. Verifying the SiP chip-set prior to manufacturing is the key milestone where these disconnects are resolved. Presented is a unique modeling, simulation and verification method which bridges these gaps much earlier in the design process. As an illustrative example the verification of a complex SiP for space applications is presented.12