Chandradevi Ulaganathan
University of Tennessee
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Chandradevi Ulaganathan.
bipolar/bicmos circuits and technology meeting | 2006
Laleh Najafizadeh; Chendong Zhu; Ramkumar Krithivasan; John D. Cressler; Yan Cui; Guofu Niu; Suheng Chen; Chandradevi Ulaganathan; Benjamin J. Blalock; Alvin J. Joseph
We present the first investigation of the optimal implementation of SiGe BiCMOS precision voltage references for extreme temperature range applications (+120 degC to -180 degC and below). We have developed and fabricated two unique Ge profiles optimized specifically for cryogenic operation, and for the first time compare the impact of Ge profile shape on precision voltage reference performance down to -180 degC. Our best case reference achieves a 28.1 ppm/ degC temperature coefficient over +27 degC to -180 degC, more than adequate for the intended lunar electronics applications
bipolar/bicmos circuits and technology meeting | 2006
Ramkumar Krithivasan; Yuan Lu; Laleh Najafizadeh; Chendong Zhu; John D. Cressler; Suheng Chen; Chandradevi Ulaganathan; Benjamin J. Blalock
We investigate, for the first time, the design and implementation of a high-slew rate op-amp in SiGe BiCMOS technology capable of operation across very wide temperature ranges, and down to deep cryogenic temperatures. We achieve the first monolithic op-amp (for any material system) capable of operating reliably down to 4.3 K. Two variants of the SiGe BiCMOS op-amp were implemented using alternative biasing schemes, and the effects of temperature on these biasing schemes, and their impact on the overall op-amp performance, is investigated
IEEE Aerospace and Electronic Systems Magazine | 2012
Ryan M. Diestelhorst; Troy D. England; Richard W. Berger; Ray Garbos; Chandradevi Ulaganathan; B.J. Blalock; Kimberly Cornett; Alan Mantooth; Xueyang Geng; Foster F. Dai; Wayne Johnson; Jim Holmes; Mike Alles; Robert A. Reed; Patrick McCluskey; Mohammad Mojarradi; Leora Peltz; Robert V. Frampton; Cliff Eckert; John D. Cressler
We have described the modeling, circuit design, system integration, and measurement of a Remote Sensor Interface (Figure 20) that took place over a span of 5 years and 8 fabrication cycles. It was conceived as part of the Multi-Chip Module (MCM) shown in Figure 21, which also includes a digital control chip for clocking, programming, and read-out. Further work beyond the scope of this was performed to validate the RSI for the extreme environmental conditions of a lunar mission, and individual blocks are presently.
midwest symposium on circuits and systems | 2008
Neena Nambiar; Chandradevi Ulaganathan; Suheng Chen; M. Hale; A. Antonacci; Benjamin J. Blalock; C.L. Britton; M.N. Ericson
A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage range of 1.2 V. The ADC architecture, comprised of a ramp generator, comparators, and a Gray code counter, is discussed along with design details of the primary blocks. Measurement data shows a differential nonlinearity of less than 0.5 LSB and an approximate accuracy of 10 bits.
midwest symposium on circuits and systems | 2008
Chandradevi Ulaganathan; Neena Nambiar; B. Prothro; Robert Greenwell; Suheng Chen; Benjamin J. Blalock; C.L. Britton; M.N. Ericson; H. Hoang; R. Broughton; Kimberly Cornett; Guoyuan Fu; H.A. Mantooth; John D. Cressler; Richard W. Berger
A instrumentation channel has been designed, implemented and tested in a 0.5-mum SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces a range of external sensors to signal processing circuits. Also, analog sampling has been implemented in the channel using a flying capacitor configuration. Measurement results show the instrumentation channel supports input signals up to 200 Hz.
european conference on radiation and its effects on components and systems | 2007
Laleh Najafizadeh; Akil K. Sutton; Bongim Jun; John D. Cressler; Tuan Vo; Omeed Momeni; Mohammad Mojarradi; Chandradevi Ulaganathan; Suheng Chen; Benjamin J. Blalock; Yuan Yao; Xuefeng Yu; Foster F. Dai; Paul W. Marshall; Cheryl J. Marshall
The effects of proton irradiation on the performance of key devices and mixed-signal circuits fabricated in a SiGe BiCMOS IC design platform and intended for emerging lunar missions are presented. High-voltage (HV) transistors, SiGe bandgap reference (BGR) circuits, a general-purpose high input impedance operational amplifier (op amp), and a 12-bit digital-to-analog converter (DAC) are investigated. The circuits were designed and implemented in a first-generation SiGe BiCMOS technology and were irradiated with 63 MeV protons. The degradation due to proton fluence in each device and circuit was found to be minor, suggesting that SiGe HBT BiCMOS technology could be a robust platform for building electronic components intended for operation under extreme environments.
international midwest symposium on circuits and systems | 2012
Chandradevi Ulaganathan; Benjamin J. Blalock; Jeremy Holleman; C.L. Britton
An ultra-low voltage, self-starting, switched-capacitor based charge pump is proposed for energy harvesting applications. The integrated linear charge pump topology presented in this work has been optimized for low-voltage start-up. The control signals for the charge-transfer switches (CTS), generated using two clock phases, reduce reverse currents and thus improve the efficiency of the converter. Adiabatic switching techniques have been employed to reduce the switching losses associated with the CTS gate control. This design has been implemented in a 130-nm CMOS process. Simulation results demonstrate a low startup voltage of 125 mV with efficiency of 62 % for a static current load of 0.1 μA.
IEEE Transactions on Nuclear Science | 2012
K. V. Tham; Chandradevi Ulaganathan; N. Nambiar; Robert Greenwell; C.L. Britton; M.N. Ericson; Jeremy Holleman; Benjamin J. Blalock
A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5- μm Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.
Vlsi Design | 2010
Chandradevi Ulaganathan; Neena Nambiar; Kimberly Cornett; Robert Greenwell; Jeremy A. Yager; Benjamin S. Prothro; Kevin Tham; Suheng Chen; Richard S. Broughton; Guoyuan Fu; Benjamin J. Blalock; C.L. Britton; M. Nance Ericson; H. Alan Mantooth; Mohammad Mojarradi; Richard W. Berger; John D. Cressler
A instrumentation channel has been designed, implemented and tested in a 0.5-mum SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces a range of external sensors to signal processing circuits. Also, analog sampling has been implemented in the channel using a flying capacitor configuration. Measurement results show the instrumentation channel supports input signals up to 200 Hz.
Archive | 2007
Chandradevi Ulaganathan