Tomoyuki Suwa

Atomically Flat Silicon Surface and Silicon/Insulator Interface Formation Technologies for (100) Surface Orientation Large-Diameter Wafers Introducing High Performance and Low-Noise Metal–Insulator–Silicon FETs

Technology to atomically flatten the silicon surface on (100) orientation large-diameter wafer and the formation technology of an atomically flat insulator film/silicon interface are developed in this paper. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200-mm-diameter wafers by annealing in pure argon ambience at 1200degC for 30 min. Atomically flat surfaces with various terrace widths and step structures are observed by atomic force microscopy. It is found that the atomic terrace width changes widely with an off angle of the wafer surface from the (100) lattice plane. It is also found that the direction of the off angle significantly affects the atomically flat surface morphology, i.e., when the directions of the off angles are parallel to the <110> directions, the step structure is composed of alternating pairs of straight and triangular steps. When the directions of the off angles are parallel to the <100> directions, the step structure is composed of only straight steps. By precise control of the off angle and the direction toward the <100> directions for a 200-mm-diameter silicon wafer, we have succeeded in fabricating an atomically flat surface with straight atomic steps and a very uniform terrace width of 140-150 nm on the entire surface of a large-diameter silicon wafer. Furthermore, it is found that only radical-reaction-based insulator film formation technology, such as oxidation utilizing oxygen radicals carried out at a low temperature (400degC ), preserves the atomic flatness of the insulator film/silicon interface. Finally, when MOSFETs are fabricated with an atomically flat interface, they exhibit near ideal subthreshold swing factors, with much smaller fluctuation, extremely lower 1/f noise, and higher MOS dielectric breakdown field intensity compared with MOSFETs fabricated with conventional technologies.

Complementary Metal–Oxide–Silicon Field-Effect-Transistors Featuring Atomically Flat Gate Insulator Film/Silicon Interface

In this paper, we demonstrate newly developed process technology to fabricate complementary metal–oxide–silicon field-effect transistors (CMOSFETs) having atomically flat gate insulator film/silicon interface on (100) orientated silicon surface. They include 1,200 °C ultraclean argon ambient annealing technology for surface atomically flattening and radical oxidation technology for device isolation, flatness recovery after ion implantation, and gate insulator formation. The fabricated CMOSFET with atomically flat interface exhibit very high current drivability such as 923 and 538 µA/µm for n-channel MOSFET (nMOS) and p-channel MOSFET (pMOS) at gate length of 100 nm when combined with very low resistance source and drain contacts, four orders of magnitude lower 1/ f noise characteristics when combined with damage free plasma processes, and one decade longer time dependent dielectric breakdown (TDDB) lifetime in comparison to devices with a conventional flatness. The developed technology effectively improves the performance of the silicon-based CMOS large-scale integrated circuits (LSI).

Densification of chemical vapor deposition silicon dioxide film using oxygen radical oxidation

Silicon dioxide (SiO2) films formed by chemical vapor deposition (CVD) were treated with oxygen radical oxidation using Ar/O2 plasma excited by microwave. The mass density depth profiles, carrier trap densities, and current-voltage characteristics of the radical-oxidized CVD-SiO2 films were investigated. The mass density depth profiles were estimated with x ray reflectivity measurement using synchrotron radiation of SPring-8. The carrier trap densities were estimated with x ray photoelectron spectroscopy time-dependent measurement. The mass densities of the radical-oxidized CVD-SiO2 films were increased near the SiO2 surface. The densities of the carrier trap centers in these films were decreased. The leakage currents of the metal-oxide-semiconductor capacitors fabricated by using these films were reduced. It is probable that the insulation properties of the CVD-SiO2 film are improved by the increase in the mass density and the decrease in the carrier trap density caused by the restoration of the Si-O net...

Very Low Bit Error Rate in Flash Memory Using Tunnel Dielectrics Formed by Kr/O2/NO Plasma Oxynitridation

The gate leakage current which influences the charge hold time of flash memories is characterized as very localized in tunnel oxide area. And the leakage current value is relatively low as the quantity of the current. In conventional test-element-group (TEG) for evaluation of this leakage current, the gate leakage current is measured in relatively large area capacitors or transistors, as a result, the localized and low gate leakage current cannot be measured. In this paper, we propose the new concept TEG in which the localized gate leakage current corresponding to the bit error in the flash memory can be measured in short time. We statistically evaluated the stress induced leakage current (SILC) of all cells in very low gate leakage current region (about 10-16 A) in the very short time (a few seconds) and easily confirmed and categorized the localized cells with the large SILC after the stress. In addition, we show that plasma oxynitridation using Kr/O2/NO gases is effective in suppressing the anomalous SILC and carrier traps by statistically evaluation of 60,000 cells in proposed array TEG.

Large-Scale Test Circuits for High-Speed and Highly Accurate Evaluation of Variability and Noise in Metal--Oxide--Semiconductor Field-Effect Transistor Electrical Characteristics

To develop a new process technology for suppressing the variability and noise in metal–oxide–semiconductor field-effect transistors (MOSFETs) for large-scale integrated circuits, accurate and rapid measurement test circuits for the evaluation of a large number of MOSFET electrical characteristics were developed. These test circuits contain current-to-voltage conversion circuits and simple scanning circuits in order to achieve rapid and accurate evaluation for a wide range of measurement currents. The test circuits were fabricated and the variabilities and noises in drain–source current, gate leakage current, and p–n junction leakage current were evaluated using a large-scale test circuit.

Angle-resolved photoelectron study on the structures of silicon nitride films and Si3N4/Si interfaces formed using nitrogen-hydrogen radicals

Soft x-ray-excited angle-resolved photoemission results for nitride films formed using nitrogen–hydrogen radicals on Si(100), Si(111), and Si(110) are reported. The data were obtained using synchrotron radiation, which allowed the Si 2p, N 1s, and O 1s levels to be investigated with the same probing depth. The following main results were obtained: (1) the Si3N4 film is covered with one monolayer of Si–(OH)3N. Its areal density is 15% smaller on Si(111) than on Si(100) and Si (110), (2) the Si3N4/Si interfaces on all three surfaces are compositionally abrupt. This conclusion is based on the observation that no Si atoms bonded with three N atoms and one Si atom were detected, and (3) the observation that the number of Si–H bonds at the Si3N4/Si(110) interface is 38%–53% larger than those at the Si3N4/Si(100) and Si3N4/Si(111) interfaces indicates a dependence of the interface structure on the orientation of the substrate.Soft x-ray-excited angle-resolved photoemission results for nitride films formed using nitrogen–hydrogen radicals on Si(100), Si(111), and Si(110) are reported. The data were obtained using synchrotron radiation, which allowed the Si 2p, N 1s, and O 1s levels to be investigated with the same probing depth. The following main results were obtained: (1) the Si3N4 film is covered with one monolayer of Si–(OH)3N. Its areal density is 15% smaller on Si(111) than on Si(100) and Si (110), (2) the Si3N4/Si interfaces on all three surfaces are compositionally abrupt. This conclusion is based on the observation that no Si atoms bonded with three N atoms and one Si atom were detected, and (3) the observation that the number of Si–H bonds at the Si3N4/Si(110) interface is 38%–53% larger than those at the Si3N4/Si(100) and Si3N4/Si(111) interfaces indicates a dependence of the interface structure on the orientation of the substrate.

Chemical Structure of Interfacial Transition Layer Formed on Si(100) and Its Dependence on Oxidation Temperature, Annealing in Forming Gas, and Difference in Oxidizing Species

The angle-resolved Si 2p photoelectron spectra arising from a interfacial transition layer formed on a Si(100) were measured with a probing depth of nearly 2 nm. The novel analytical procedure of these spectra was developed by considering that one SiO2 monolayer, two compositional transition layers (CTLs), and one Si monolayer constituting the Si substrate surface are continuously connected with each other to maintain the areal density of Si atoms. It was found for thermally grown transition layers that two CTLs are formed on the oxide side of the CTL/Si interface and the chemical structures correlated with the residual stress appear on the Si substrate side of the interface. The effects of oxidation temperature in the range from 900 to 1050 °C, annealing in the forming gas, and oxidation using oxygen radicals on the chemical structures of transition layers formed on both sides of the interface were also clarified.

Crystallographic orientation dependence of compositional transition and valence band offset at SiO2/Si interface formed using oxygen radicals

The chemical and electronic-band structures of SiO2/Si interfaces formed utilizing oxygen radicals were investigated by measuring angle-resolved photoelectron spectra arising from Si 2p and O 1s core levels and a valence band with the same probing depth. We clarified that (1) the SiO2/Si interfaces formed exhibited an almost abrupt compositional transition, (2) the valence band offsets at the Si(111)/Si, Si(110)/Si, and Si(551)/Si interfaces are almost the same and are 0.07 eV smaller than that at the SiO2/Si(100) interface.

Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate–source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

Depth Profile of Nitrogen Atoms in Silicon Oxynitride Films Formed by Low-Electron-Temperature Microwave Plasma Nitridation

Angle-resolved photoelectron spectroscopy study was performed on the depth profile of nitrogen atoms in silicon oxynitride (SiON) films formed by the plasma nitridation of silicon dioxide using low-electron-temperature microwave plasma. The depth profile of nitrogen near the SiON surface was confirmed to increase and its peak position moves into SiON films with an increase in the nitridation time, which improves boron immunity. A new transport and reaction model of plasma nitridation is proposed to explain the time evolution of nitrogen concentration and its depth profile in the films. Here, the density of radical nitrogen atoms decreases exponentially with an increase in the distance from the surface, and the nitrogen concentration incorporated in the SiON film is approximately proportional to the logarithmic time of plasma nitridation. It was newly found that post-nitridation annealing strongly enhances the pile-up of nitrogen atoms at the Si–SiON interface owing to their diffusion from the inward tail of the nitrogen depth profile near the surface. It is deduced that the pile-up of nitrogen atoms induces Si–H bonds at the interface, which become the main trigger for the degradation of the negative bias temperature instability of p-channel metal–oxide–silicon transistors.