Rita Verbeeck

Electrical-transport in (100)CoSi2/Si contacts.

A detailed investigation of the electrical transport in (100) CoSi2/Si contacts is presented. The transport properties of epitaxial CoSi2 films, obtained both by ion‐beam synthesis and by solid‐state reaction of a Ti/Co bimetallic layer, are compared with the transport properties of conventional polycrystalline CoSi2 layers. The electrical resistivity, the magnetoresistance, and the Hall effect are measured on Hall bars for temperatures ranging from 1.2 to 300 K and magnetic fields up to 5 T. Very high values of the order parameter kFL0 are observed, indicating that the investigated samples are of very high purity and crystalline order. In addition, the electric transport at the CoSi2/Si interface is studied by current‐voltage and capacitance‐voltage measurements on Schottky diode structures for temperatures ranging from 173 to 333 K. Ideality factors close to unity are observed for the highest temperatures, for the lower temperatures the ideality factors are found to increase with decreasing temperatures...

Thermal Stability of CoSi 2 on Submicron Polycrystalline Silicon Lines

The thermal stability of CoSi2 layers on undoped, B- and As-doped, submicron-sized polycrystalline Si lines has been investigated. It is found that the highest thermal stability is obtained for undoped poly-Si lines. The thermal stability of the silicide layers on As- or B-doped lines is largely improved if an additional Ge implant is performed prior to Co sputtering which amorphizes the complete Si layer which is consumed during silicidation.

A manufacturable process to improve thermal stability of 0.25-/spl mu/m cobalt silicided poly gate

A CoSi/sub 2/ salicidation process using a thin titanium capping layer is developed to improve the thermal stability of deep submicron CoSi/sub 2//poly stacks. 50 nm CoSi/sub 2/ was uniformly formed on 0.25-/spl mu/m wide poly lines. The electrical results show that the lines formed by a capping process using Ti can withstand higher thermal treatment (750/spl deg/ C for 30 min) without significant degradation. This work shows that the modified CoSi/sub 2/ process should be considered for 0.25-/spl mu/m CMOS applications. >

Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

Short gate-length Pt full-silicidation (FUSI) (PtSi and Pt2 Si) pMOSFETs were fabricated for the first time using a self-aligned Pt-FUSI process, demonstrating scalability (with no linewidth effects) down to ~ 60-nm gate lengths. The electrical results are compared to the Ni-FUSI (NiSi and Ni31Si12) pMOSFET devices. A low threshold voltage les|-0.29 V| was obtained for the Pt2Si-FUSI pMOSFETs on SiON and HfSiON indicating that the Pt2Si FUSI does not suffer from the Fermi-level pinning or gate-dielectric-charge effects on the HfSiON

Etching of CoSi2 in HF-based solutions

Abstract The etching of CoSi 2 thin films in hydrogen fluoride (HF) based solutions has been investigated. It has been observed that the etching mechanism follows a layer-by-layer removal, with a constant etch rate. It has been found that the etch rate of cobalt disilicide in a HF 2 wt% solution is very dependent on the pH of the solution. The lower the pH value is, i.e. a more acid mixture, the higher the etch rate is. CoSi 2 etching in HF-based solutions is controlled predominantly by the H + concentration.

Two-step anneals to avoid bridging during Co silicidation

Abstract A two-step rapid thermal process has successfully been applied for the simultaneous Co silicidation of source/drain and gate areas in MOS test structures while avoiding lateral creep or bridging. The method is based on the formation of CoSi on the active areas and poly-Si gate lines during the first RTP step, while keeping the thermal budget sufficiently low in order not to form this silicide phase on the spacers. Following a selective etch, a second RTP step leads to the formation of CoSi2. After sputtering of 20 nm Co on either undoped or doped wafers, RTP was done at 487°C for 30 s to form CoSi. A subsequent selective etch and a second RTP step heating the wafer up to 850°C, resulted in a sheet resistance of 3–6Ω/□ on both the active areas and poly-Si gate lines. A “non-bridging” yield, which is in all cases close to 100%, has been found, irrespective of the considered processing parameters.

Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics

In this work, we present a methodology for characterizing the impact of circuit layout style, technology elements (low-k material, resist choice), device engineering and temperature on the circuit power-delay trade-off. We provide experimental results supported by modeling work, showing significant improvements in circuit speed at fixed power levels resulting from improvements in layout style and technology. For instance, the use of a more advanced resist at gate level leads to a 3/spl times/ reduction in static power dissipation at a given ring-oscillator (RO) delay or in other words close to a 10% improvement in the inverter delay for a similar static power dissipation.

FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production

The integration of fully silicided gates on a high-k dielectric in a standard process flow offers a solid alternative to the conventional Poly/SiON devices. In this work, we provide an extensive analysis of the module yield extracted for such devices highlighting the need for specific additional alarm flags without which some integration problems might be overlooked. The impact at the circuit level is studied and supported by modeling work on simple ring-oscillators.

On the formation of silicides on poly runners with topography by a two-step silicidation process

The formation of titanium and cobalt silicide on poly runners with topography is studied in this work. Poly runners with various topography heights and slopes were silicided by a two-step salicide process and inspected by SEM and electrical measurements. Even though the topography was more severe than in current PBLOCOS processes, no electrical defects in the continuity of the silicide were observed. Cross-section SEM reveals, however, that the metal coverage on the steps plays a major role in the continuity of the silicide formed.