Philippe Jansen

Substrate bonding techniques for CMOS processed wafers

Transferring a CMOS circuit to a foreign substrate can be accomplished by bonding a processed silicon wafer to the substrate and subsequently thinning the silicon wafer. This paper presents both anodic bonding and adhesive bonding and evaluates their potential for circuit transfer.

Lithography Options for the 32 nm Half Pitch Node and Beyond

Three major technological lithography options have been reviewed for high volume manufacturing at the 32 nm half pitch node: 193 nm immersion lithography with high index materials, enabling NA > 1.6; 193 nm double patterning and EUV lithography. In this paper the evolution of these three options over 2008 is discussed. The extendibility of these options beyond 32 nm half pitch is important for the final choices to be made. During 2008, the work on high index 193 nm immersion lithography has been stopped due to lack of progress in high index optical material and high index liquid development. Double patterning has made a lot of progress but cost concerns still exist. Preferred are those resists which support pattern or image freezing techniques in order to step away from the complex litho-etch-litho-etch approach and make double patterning more cost effective. For EUV, besides the high power light source, the resist materials need to meet very aggressive sensitivity specifications and need to maintain simultaneously performance in terms of resolution and line width roughness. Furthermore, EUV reticles encounter serious challenges, primarily related to mask defectivity.

Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides

Optimum device design for high performance applications has been investigated assuming a fixed oxide thickness of 2.5 nm and supply voltage of 1.5 V. The optimal performance is achieved by minimizing parasitic effects. The influence of experimental splits in source/drain (S/D) extension dose, S/D HDD dose and spike RTA on the reduction of series resistance and poly-depletion effect is studied. The role of the HALO implantation in optimization is investigated in detail.

Snapback circuit model for cascoded NMOS ESD over-voltage protection structures

This paper presents an equivalent circuit snapback model for the ESD domain operation of merged cascoded NMOS devices. The model reflects the specific breakdown operation of the structure at different gate bias conditions. An example for optimisation of the ESD behaviour of an output driver, utilising this protection device, is presented.

Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications

Charged device model (CDM) electrostatic discharge (ESD) stress is a major concern for inductor-based ESD protection strategies for RF circuits processed in advanced nano-CMOS technologies. The CDM robustness of such protection methodology is investigated in this paper based on very-fast transmission line pulse (VFTLP) measurements. Its applicability is discussed for future technologies and RF applications.

AlGaAs/GaAs: High electron mobility transistor simulations with PRISM

The two-dimensional device simulator PRISM (PRogram for Investigating Semiconductor Models) [1], which is a general purpose device simulator, has been adapted to simulate III-V heterojunction FETs [2]. PRISM can now simulate silicon devices (as MOSFETs, bipolar transistors, SO1 structures, etc.,), GaAs MESFETs, Schottky diodes and AIGaAsl GaAs HEMTs. The program makes use of the finite element method to solve the Poisson equation and the finite boxes method to solve the continuity equations for electrons and holes. There is also an ongoing effort to implement the heat transport equation [3]. The finite element method has rarely been used in HEMT-simulations. The main advantages of this method are the flexibility in defining sloped device contours and the possibilic to refine the mesh only locally, so that the number of nodes only increases moderately, as opposed to the situation with finite difference simulators. This advantage is very usefull for HEMTs were the thin AlGaAs/GaAs heterojunction region ( 40 nm) has to be simulated accurately compared to the bulk region. Simulations of AlGaAslGaAs HEMTs have been performed, and comparisons with measurements on HEMTs [4] processed in IMEC have been made. The simulated I-V characteristics and the transconductance curves agree very well. Also sheet concentrations and band diagrams can be extracted from the simulation results.

Non-Alloyed Ge/Pd Contacts for AlAs/GaAs Resonant Tunneling Structures

Resonant AlAs/GaAs/AlAs tunneling diodes with very thin top contact layers have been fabricated using non-alloyed Ge/Pd/n ohmic contacts. The current-voltage characteristics of a set of resonant tunneling diodes that only differed in the thickness of the top contact layer clarify the action range of separate processes taking place during contact formation. Resonant tunneling performance is still observed in structures with contact layers as thin as 10 nm. Device applications that require the contacting of a very thin layer can therefore benefit most from this contact scheme.

A Resonant Tunneling High Electron Mobility Transistor

A double barrier resonant tunneling heterostructure has been combined with a pseudomorphic high electron mobility transistor. This three terminal device shows negative transconductance in addition to a clear negative differential resistance region which shifts with gate voltage. The device characteristics can be adequately explained by a simple device simulation model. Flip-flop and frequency doubling operations at room temperature are demonstrated.