Robert C. Taft

A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 /spl mu/m/sup 2/ with conventional I-line lithography and 7.32 /spl mu/m/sup 2/ with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 /spl mu/m active pitch, MOSFET transistors designed for a 0.80 /spl mu/m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance. >

Optimization of two-dimensional collector doping profiles for submicron BiCMOS technologies

The authors demonstrate that the optimal 2-D collector doping profile for BiCMOS technologies is a strong function of the intended circuit application of the BJT (bipolar junction transistor). The 2-D collector doping profile in this study was tailored by selectively implanting the collector (SIC) into only the intrinsic region of the BJT. A controlled comparison between SIC and conventional collector implant devices was made by keeping BV/sub CEO/ and beta invariant. It is concluded that selectively implanting the collector into the intrinsic area is advantageous for low-current, but detrimental for high-current gates.<<ETX>>

Ge/sub x/Si/sub 1-x//silicon inversion-base transistors: experimental demonstration

The fabrication, material characterization, and electrical evaluation of the p-channel Ge/sub x/Si/sub 1-x//silicon inversion-base transistor (BICFET) are described. The BICFET was one of the first bipolar devices to take advantage of the breakthroughs in advanced Ge/sub x/Si/sub 1-x//Si processing technology, to which its p-channel implementation is ideally suited. At this time, the performance limitations of the Ge/sub x/Si/sub 1-x//Si BICFET are set only by the current fabrication technology, and not by limits imposed by its physical principles of operation. The electrical results presented include both the unipolar characteristics, in which the BICFET is configured as a heterojunction FET, and the bipolar characteristics, which is the intended high-performance mode of operation. The experimental results presented are in good agreement with theoretical study. >

Ge/sub x/Si/sub 1-x//silicon inversion-base transistors: theory of operation

A theoretical study of the device characteristics of the Ge/sub x/Si/sub 1-x//silicon inversion-base transistor (BICFET) is presented. This transistor uses the space charge of holes in a modulation-doped inversion channel to control vertical electron transport. This study is of interest not only because of the unique interaction of transport mechanisms in the BICFET but also because the BICFET is very well suited to the Ge/sub x/Si/sub 1-x//Si system, and offers substantial performance advantages over the BJT. The device characteristics presented are based on a numerical and analytical analysis using the drift-diffusion formalism. The effects that quantum confinement and non-semi-classical transport have on this structure are presented. The authors conclude with a comparison between the Ge/sub x/Si/sub 1-x//Si BICFET and Ge/sub x/Si/sub 1-x//Si HBT. >

The SCC BJT: a high-performance bipolar transistor compatible with high-density deep-submicrometer BiCMOS SRAM technologies

We present the process development and device characterization of the Selectively Compensated Collector (SCC) BJT specifically designed for high-density deep-submicrometer BiCMOS SRAM technologies. This double-poly BJT takes advantage of the self-aligned polysilicon layers of the SRAM bit cell to obtain high performance without adding excessive process complexity. Furthermore, although an NPN device, the SCC BJT is formed in a lightly doped p-well in which the collector is formed with a single 370 keV phosphorus implant to minimize parasitic junction capacitances without the use of trench isolation or recessed oxides. The suitability of this bipolar structure outside of its original FSRAM intent is proven with its potential for bipolar logic and mixed-mode RF applications. ECL delays of 50 ps at 200 /spl mu/A and a CML power-delay product of 4.5 fJ at 1.1 V supply were obtained. A 900 MHz noise figure as low as 0.54 dB at 0.5 mA with an associated gain of 14.7 dB was demonstrated as well as a dual modulus /spl divide/4/5 prescaler operating up to 3.3 GHz for a switch current of 200 /spl mu/A. >