Robert J. Chiu

Efficient and cost-effective photo defect monitoring

Manufacturing processes for submicron integrated circuits require strict process control for minimizing defects during the fabrication process. Defect densities are monitored on product wafers to determine whether the line maintains an acceptable yield level and to prevent any catastrophic downfall. However, defect detection is difficult for multilayer devices. A short loop defect monitor is often employed in the Photolithography area for inspection on an automated wafer inspection system like the KLA 213x. This monitor usually uses clean bare Silicon wafers which are processed through a Photocluster cell to define a resist pattern for defect inspection. In order to monitor a large set of equipment and resist types, a large quantity of clean Silicon wafers are required. The reuse of these silicon photo monitor wafers becomes difficult due to particles left on wafers after resist clean. Thus, the cost of daily photo defect monitor for equipment/process control becomes considerable. In this paper, we will discuss reusable thermal oxide test wafers as an alternative solution to Si wafers for a cost effective photo defect monitor. The required oxide thickness for I-line and DUV resists was calculated from Prolith/2 simulation. By using a special clean with Sulfuric Acid/Hydrogen Peroxide mixture (SPM) and followed by an Ammonium Hydroxide/Hydrogen Peroxide mixture (APM) for resist strip, very low particle counts were achieved for oxide substrate and better than those of Silicon wafers. Furthermore, due to low oxide thickness loss per clean cycle (1 - 2 A), oxide test wafers retain the optical characteristics for defect metrology tools to work without any recalibration. This makes the oxide photo defect monitor process very robust and production worthy. KLA defect data on unpatterned and patterned oxide test wafers for 20 or more reworks, will be shown. They will be compared to control Silicon test wafers. Some issues with exposure and focus condition and their effect on KLA defect detection will be discussed. Finally, a simple cost analysis model will show the potential saving benefit of oxide test wafer.

Single closed contact for 0.18-micron photolithography process

With the rapid advances of deep submicron semiconductor technology, identifying defects is converted into a challenge for different modules in the fabrication of chips. Yield engineers often do bitmap on a memory circuit array (SRAM) to identify the failure bits. This is followed by a wafer stripback to look for visual defects at each deprocessed layer for feedback to the Fab. However, to identify the root cause of a problem, Fab engineers must be able to detect similar defects either on the product wafers in process or some short loop test wafers. In the photolithography process, we recognize that the detection of defects is becoming as important as satisfying the critical dimension (CD) of the device. For a multi-level metallization chemically mechanical polish backend process, it is very difficult to detect missing contacts or via at the masking steps due to metal grain roughness, film color variation and/or previous layer defects. Often, photolithography engineer must depend on Photo Cell Monitor (PCM) and short loop experiments for controlling baseline defects and improvement. In this paper, we discuss the findings on the Poly mask PCM and the Contact mask PCM. We present the comparison between the Poly mask and the Contact mask of the I-line Phase Shifted Via mask and DUV mask process for a 0.18 micron process technology. The correlation and the different type of defects between the Contact PCM and the Poly Mask are discussed. The Contact PCM was found to be more sensitive and correlated to contact failure at sort yield better. We also dedicate to study the root cause of a single closed contact hole in the Contact mask short loop experiment for a 0.18 micron process technology. A single closed contact defect was often caused by the developer process, such as bubbles in the line, resist residue left behind, and the rinse mechanism. We also found surfactant solution helps to improve the surface tension of the wafer for the developer process and this prevents/eliminates a single closed contact hole defects. The applications and effects of using different substrates like SiON, different thicknesses of Oxides, and Poly in the Contact Photo Mask is shown. Finally, some defect troubleshooting techniques and the root cause analysis are also discussed.