Robert Paiz

Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof

High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers

Method and apparatus for in-situ cleaning of polysilicon-coated quartz furnaces

Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode

Small gate electrode MOSFET

Method for in-situ cleaning of polysilicon-coated quartz furnaces

Multilevel transistor fabrication method having an inverted, upper level transistor

Method of manufacturing a semiconductor device by doping an active region after formation of a relatively thick oxide layer

Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions

Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths