Rocío del Río
University of Seville
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Featured researches published by Rocío del Río.
Archive | 2013
José M. de la Rosa; Rocío del Río
This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations # going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues – from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence Design FrameWork II. As well as being a comprehensive reference to the theory, the book is also unique in that it gives special importance on practical issues, giving a detailed description of the different steps that constitute the whole design flow of sigma-delta ADCs.
Microelectronics Journal | 2009
José M. de la Rosa; R. Castro-López; Alonso Morgado; Edwin C. Becerra-Alvarez; Rocío del Río; Francisco V. Fernández; B. Perez-Verdu
The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical. These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems.
IEEE Transactions on Circuits and Systems | 2004
Rocío del Río; José M. de la Rosa; B. Perez-Verdu; Manuel Delgado-Restituto; R. Dominguez-Castro; Fernando Medeiro; Ángel Rodríguez-Vázquez
We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator.We present a 90-dB spurious-free dynamic range sigma-delta modulator M) for asymmetric digital subscriber line applications (both ADSL and ADSL ), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25- m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band ADSL and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within 0.85 and 0.80 LSB b , respectively. The modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the modulator.
Sensors | 2014
Jorge Fernández-Berni; Ricardo Carmona-Galán; Rocío del Río; Richard P. Kleihorst; Wilfried Philips; Ángel Rodríguez-Vázquez
The capture, processing and distribution of visual information is one of the major challenges for the paradigm of the Internet of Things. Privacy emerges as a fundamental barrier to overcome. The idea of networked image sensors pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. Power consumption also constitutes a crucial aspect. Images contain a massive amount of data to be processed under strict timing requirements, demanding high-performance vision systems. In this paper, we describe a hardware-based strategy to concurrently address these two key issues. By conveying processing capabilities to the focal plane in addition to sensing, we can implement privacy protection measures just at the point where sensitive data are generated. Furthermore, such measures can be tailored for efficiently reducing the computational load of subsequent processing stages. As a proof of concept, a full-custom QVGA vision sensor chip is presented. It incorporates a mixed-signal focal-plane sensing-processing array providing programmable pixelation of multiple image regions in parallel. In addition to this functionality, the sensor exploits reconfigurability to implement other processing primitives, namely block-wise dynamic range adaptation, integral image computation and multi-resolution filtering. The proposed circuitry is also suitable to build a granular space, becoming the raw material for subsequent feature extraction and recognition of categorized objects.
european solid-state circuits conference | 2010
Alonso Morgado; Rocío del Río; José M. de la Rosa; Lynn Bos; Julien Ryckaert; Geert Van der Plas
This paper presents an adaptive 1.2-V 90-nm CMOS cascade two-stage (2–2) SC ΣΔ modulator with 3-level quantization and unity signal transfer function in both stages. The chip reconfigures its loop filter order (either 2nd or 4th-order), clock frequency (from 40 to 240 MHz) and scales power according to the required specifications for different wireless standards, covering: GSM, Bluetooth, GPS, UMTS, DVB-H and WiMAX. Measurements feature a dynamic range of 78/70/71.5/66/62/52dB and a peak signal-to-(noise+distortion) ratio of 72.3/68.0/65.4/63.3 /59.1/48.7dB within 100kHz/500kHz/1MHz/2MHz/4MHz/10MHz, while consuming 4.6/5.35/6.2/8/8/11mW, respectively. These results show a competitive performance with the state-of-the-art multi-standard ΣΔ modulators, covering one of the widest regions in the DR-vs.-Bandwidth plane†1.
International Journal of Circuit Theory and Applications | 2015
Jorge Fernández-Berni; Ricardo Carmona-Galán; Rocío del Río; Ángel Rodríguez-Vázquez
Summary Focal-plane mixed-signal arrays have traditionally been designed according to the general claim that moderate accuracy in processing is affordable. The performance of their circuitry has been analyzed in these terms without a comprehensive study of the ultimate consequences of such moderate accuracy. In this paper, for the first time to the best of our knowledge, we do carry out this study. We move expectable performance of mixed-signal image processing hardware directly into the vision algorithm making use of it. This permits to close a wider design loop, enabling a more aggressive design of this kind of hardware provided that the algorithm, at the highest level—semantic interpretation of the scene—, can afford it. Thus, we present a thorough analysis of the non-idealities associated with the implementation of a QVGA array tailored for the distinctive characteristics of the Viola–Jones processing framework. The resulting deviation models are then introduced in the processing flow of this framework provided by the OpenCV library. We have found, contrary to what could be expected, that these deviations do not necessarily degrade the performance of the Viola–Jones algorithm. They could be even beneficial for certain high-level specifications. Additionally, we demonstrate the architectural advantages of our approach: exploitation of focal-plane distributed memory and ultra-low-power operation. Copyright
Analog Integrated Circuits and Signal Processing | 2004
José M. de la Rosa; B. Perez-Verdu; Fernando Medeiro; Rocío del Río; Ángel Rodríguez-Vázquez
This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass ΣΔM (2nd-LPΣΔM) and a 4th-order BandPass ΣΔM (4th-BPΣΔM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notchfrequency position in the case of 4th-BPΣΔMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI ΣΔMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 μm CMOS SI 4th-BPΣΔM silicon prototype validate our approach.
Microelectronics Journal | 2010
Alonso Morgado; Rocío del Río; José M. de la Rosa; R. Castro-López; B. Perez-Verdu
This paper describes the design and experimental characterization of a 0.13@mm CMOS switched-capacitor reconfigurable cascade @S@D modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80MHz), the internal quantization (1 or 2bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7dB at 400ksps/2/8Msps, respectively. The modulator power consumption is 23.9/24.5/44.5mW, of which 9.7/10/24.8mW are dissipated in the analog circuitry. The multi-mode @S@D prototype shows an overall performance that is competitive with the current state of the art.
international symposium on circuits and systems | 2009
José M. de la Rosa; Alonso Morgado; Rocío del Río
This paper presents novel architectures of hybrid continuous-time/discrete-time cascade ΣΔ modulators that combine the benefits of both circuit techniques with programmable noise transfer function resonation and unity signal transfer function in all stages. Both local and inter-stage based resonation topologies are synthesized and compared in terms of their circuit complexity, resolution-bandwidth programmability and robustness with respect to circuit implementation. As an application, a multi-standard case study is presented, targeting 5–14 bit programmable effective resolution within a tunable 100kHz–100MHz signal bandwidth.
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) | 2012
Sohail Asghar; Rocío del Río; José M. de la Rosa
This paper describes the design of a switched-capacitor fourth-order single-loop ΣΔ modulator with a 5-level embedded quantizer. The loop filter consists of a cascade of resonators with distributed feedforward coefficients, which can be programmed to make the zeros of the noise transfer function variable. As a result, the modulator can be reconfigured either as a lowpass or as a bandpass analog-to-digital converter with a tunable notch frequency and an optimized loop-filter zero placement. The circuit - designed and implemented in a 1.2-V 90-nm CMOS technology - incorporates diverse architecture- and circuit-level strategies to adapt its performance to different sets of specifications with a variable sampling frequency of 100 and 200MHz and scalable power consumption. Post-layout simulations (for a frequency range of DC to 22MHz) and behavioral simulations (from 22 to 44MHz) show a correct operation of the circuit in steps of 1-to-2MHz, featuring an adaptive SNDR of 74-to-86, 57-to-68 and 50-to-59dB within a signal bandwidth of 200kHz, 1MHz and 2MHz, respectively, while dissipating a scalable power consumption of 16-to-22mW*.