Alonso Morgado

A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP

This paper presents a MUlti-SEnsor biomedical IC (MUSEIC). It features a high-performance, low-power analog front-end (AFE) and fully integrated DSP. The AFE has three biopotential readouts, one bio-impedance readout, and support for general-purpose analog sensors The biopotential readout channels can handle large differential electrode offsets ( ±400 mV), achieve high input impedance ( >500 M Ω), low noise ( 620 nVrms in 150 Hz), and large CMRR ( >110 dB) without relying on trimming while consuming only 31 μW/channel. In addition, fully integrated real-time motion artifact reduction, based on simultaneous electrode-tissue impedance measurement, with feedback to the analog domain is supported. The bio-impedance readout with pseudo-sine current generator achieves a resolution of 9.8 m Ω/ √Hz while consuming just 58 μW/channel. The DSP has a general purpose ARM Cortex M0 processor and an HW accelerator optimized for energy-efficient execution of various biomedical signal processing algorithms achieving 10 × or more energy savings in vector multiply-accumulate executions.

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ.

Adaptive CMOS analog circuits for 4G mobile terminals-Review and state-of-the-art survey

The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical. These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems.

LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency

This paper analyses the use of bandpass continuous-time ΣΔ modulators with widely programmable notch frequency for the efficient digitization of radio-frequency signals in the next generation of software-defined-radio mobile systems. The modulator architectures under study are based on a fourth-order loop filter - implemented with two LC-based resonators - and a finite-impulsive-response feedback loop in order to increase their flexibility and degrees of freedom. Several topologies are studied, considering three different cases for the embedded digital-to-analog converter, namely: return-to-zero, non-return-to-zero and raised-cosine waveform. In all cases, a notch-aware synthesis methodology is presented, which takes into account the dependency of the loop-filter coefficients on the notch frequency and compensates for the dynamic range degradation due to the variation of the notch. The synthesized modulators are compared in terms of their sensitivity to main circuit error mechanisms and the estimated power consumption over a notch-frequency tuning range of 0.1fs to 0.4fs. Time-domain behavioral and macromodel electrical simulations validate this approach, demonstrating the feasibility of the presented methodology and architectures for the efficient and robust digitization of radio-frequency signals with a scalable resolution and programmable signal bandwidth.

A 100kHz–10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS

This paper presents an adaptive 1.2-V 90-nm CMOS cascade two-stage (2–2) SC ΣΔ modulator with 3-level quantization and unity signal transfer function in both stages. The chip reconfigures its loop filter order (either 2nd or 4th-order), clock frequency (from 40 to 240 MHz) and scales power according to the required specifications for different wireless standards, covering: GSM, Bluetooth, GPS, UMTS, DVB-H and WiMAX. Measurements feature a dynamic range of 78/70/71.5/66/62/52dB and a peak signal-to-(noise+distortion) ratio of 72.3/68.0/65.4/63.3 /59.1/48.7dB within 100kHz/500kHz/1MHz/2MHz/4MHz/10MHz, while consuming 4.6/5.35/6.2/8/8/11mW, respectively. These results show a competitive performance with the state-of-the-art multi-standard ΣΔ modulators, covering one of the widest regions in the DR-vs.-Bandwidth plane†1.

A design methodology for power-efficient reconfigurable SC ΔΣ modulators

Summary This paper presents a methodology to design reconfigurable switched-capacitor delta-sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low-bandwidth, medium-to-high-resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power-optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade-off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18-µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach. Copyright

A 155 /spl mu/W 88-dB DR Discrete-Time /spl Delta/ /spl Sigma/ Modulator for Digital Hearing Aids Exploiting a Summing SAR ADC Quantizer

This paper presents a low-power switched-capacitor ΔΣ modulator for digital hearing-aid applications that features a novel summing successive approximation (SAR). The summing SAR performs multi-bit quantization together with the analog addition required in feed-forward (FF) ΔΣ modulator (ΔΣM) topologies, with no attenuation of the input signals and no need for amplifiers. The prototype is implemented in a 0.18- μm CMOS technology and its measurements demonstrate a dynamic range of 88 dB in 10 kHz bandwidth while consuming 155 μW from a 1.8 V supply. The combined use of passive addition and SAR quantization reduces the complexity and power consumption of the modulator. The summing SAR ADC quantizer results in a calculated power saving of 40% when compared to a multi-bit FF ΔΣM using active addition and flash quantization.

High-Efficiency Cascade

This paper overviews a number of ΣΔ modulation techniques to implement efficient analog-to-digital converters intended for low-voltage wideband multimode wireless telecom systems. The ΣΔ architectures under study combine different strategies-unity signal transfer function (USTF), resonation, loop-filter order reconfiguration, and concurrency-in order to increase performance while keeping high robustness against circuit errors. Practical considerations involving timing issues-derived from the combined use of different noise-shaping techniques-are analyzed in order to evaluate the feasibility of the proposed ΣΔ topologies. As an application, the design, circuit implementation, and experimental characterization of a flexible 1.2-V 90-nm CMOS sixth-order three-stage cascade SC ΣΔ modulator is presented. The modulator uses local resonation in the last two stages and USTF and programmable (either three or five levels) quantization in all stages. The chip reconfigures its loop-filter order (second, fourth, sixth order) and the clock frequency (from 40 to 240 MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental measurements show the flexibility of the proposed circuit, featuring a programmable noise shaping within a 100-kHz-10-MHz signal band, with adaptive power dissipation, thus demonstrating to be a suitable solution to digitize signals in future software-defined-radio mobile terminals.

\Sigma\Delta

This paper describes the design and experimental characterization of a 130-nm CMOS cascade SigmaDelta modulator intended for multi-standard wireless telecom systems. Both architectural-and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt its performance to different standard specifications with optimized power dissipation. Measurements show a correct operation for GSM/Blue-tooth/WCDMA standards, featuring a dynamic range of 86.7/81.0/63.3dB and a peak signal-to-(noise+distortion) ratio of 74.0/68.4/52.8 dB within 200kHz/1MHz/4MHz, respectively. The power consumption is 25.2/25.0/44.5 mW, of which 11.0/10.5/24.8 are due to the analog part of the circuit+1.

Modulators for the Next Generation Software-Defined-Radio Mobile Systems

This paper presents design considerations for cascade sigma-delta modulators (SAMs) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1L-2 expandible SigmaDeltaM is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach