Roman Boschke

SOI device having a substrate diode formed by reduced implantation energy

SOI DEVICE WITH A BURIED INSULATING MATERIAL HAVING INCREASED ETCH RESISTIVITY

Method for self-aligned removal of a high-k gate dielectric above an sti region

Verfahren zur Herstellung verformter Transistoren durch Verspannungskonservierung auf der Grundlage einer verspannten Implantationsmaske

Soi transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern

Temperaturüberwachung in einem Halbleiterbauelement durch Thermoelemente, die in der Kontaktstruktur verteilt sind

Verfahren zum selbstjustierten Entfernen eines Gatedielektrikums mit großem ε über einem STI-Gebiet

Semiconductor device i.e. integrated circuit, manufacturing method for e.g. microprocessor, involves removing part of deformation inducing layer from above transistor under application of dielectric layer as etch-stopping material

Semiconductor device having a high-K gate dielectric above an STI region