Casey Scott

Multiple Stress Memorization In Advanced SOI CMOS Technologies

Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent of the crystalline state of the Si. Both improve NMOS drive current, and the resulting improvements are additive to >27% NMOS IDSAT improvement. The first phenomenon is previously unreported. It has been identified to be localized in the source/drains, and yields more improvement with multiple offset implantation prior to capping and annealing.

Material choice for optimum stress memorization in SOI CMOS processes

Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique for SOI CMOS transistors. We distinguish between low- and high-temperature stress memorization. Film hardness, stress level, and the order of anneals are found to play an important and partially very different role for these two improvement mechanisms.