Ron Zhang

Characterization of microprocessor chip stress distributions during component packaging and thermal cycling

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.

Substantiation of numerical analysis methodology for CPU package with non-uniform heat dissipation and heat sink with simplified fin modeling

Thermal design in electronic packaging is driven by the maximum allowable junction temperature of a CPU. An inadequate thermal design that underestimates the junction temperature may adversely impact the electrical performance of the CPU, making predicting the junction temperature a crucial step in package and system thermal design. A numerical model of a heat sink and thermal test package with a uniform and non-uniform power dissipation was created and used to predict their temperatures. The uniform power dissipation case was used to calibrate the numerical models TIM2 thermal impedance. In the non-uniform power cases, the maximum heat flux was over four times higher than the average heat flux. The numerical analysis results in the non-uniform power cases yielded junction temperatures within 2 degrees of the measured values. The heat sink used in the tests as well as numerically modeled contained a vapor chamber base and a plate heat sink. Three different heat sink modeling approaches were used, including: detailed modeling of the heat sink, effective convection coefficient heff, and effective thermal conductivity keff. Test data was used to establish the effective heat transfer coefficient and effective thermal conductivity. A simplified heat sink numerical model allows the computational grid density to be significantly reduced, resulting in fast convergence. Alternate heat sink designs were also considered.

Characterization of board level reliability of a system with flip chip HITCE BGA package through modeling and testing

Flip chips with ceramic substrates have traditionally been favored in high performance packages for their excellent solder bump fatigue reliability due to the close CTE match between the substrate and the silicon die. To mitigate the impact of large CTE mismatch on board level reliability, Land grid array(LGA) sockets can be used. However, demands for high current carrying capability and high I/O counts limit LGA applications. With the introduction of HITCE glass ceramic substrates, direct solder attach of BGA packages to PCBs becomes possible. Although there is a growing body of test data on board level reliability, no work on fatigue life prediction has been published, particularly with lead-free SAC alloys. This paper bridges the gap by using finite element modeling (FEM) to first predict fatigue life and then comparing model predictions with test data. The impacts of various design parameters are explored after initial model validations.

Stress measurements in large area array flip chip microprocessor chips

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher level of power generation, and larger heat sinks. Die stress effects are of concern due to the possible degradation of silicon device performance (mobility/speed) and due to the possible damage that can occur to the copper/low-k top level interconnect layers. In this work, we have used test chips containing piezoresistive sensors to measure the stresses induced in microprocessor die after various steps of the assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the stress test die. The chips were reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level.

Measurement of die stress distributions in flip chip CBGA packaging

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as the stress changes occurring due to thermal cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers.

Wafer level LED packaging with optimal light output and thermal dissipation for high-brightness lighting

Market size of high-brightness LED lighting has been rapidly growing upon the continual improvement of quantum efficiency and light extraction. However some key breakthroughs must be made before this technology can be fully adopted into the broad market, such as efficient thermal dissipation and low manufacturing cost. A major portion of cost of an LED module falls in the packaging processes after the emissive device stack has been fabricated. Also given the thin thickness of device stack, the packaging structure holds the bottleneck for thermal dissipation. We address these two key challenges with a novel wafer-level packaging structure integrated into the device stack, which enables maximal thermal dissipation rate from active device stack to substrate while allowing high aperture ratio and optimal light output. Our approach applies full wafer-level batch process from epitaxial growth all the way down to packaging for light extraction and wavelength conversion, in order to achieve high throughput and high yield at low cost. Initial prototypes of GaN based blue LED with big chip size have been fabricated without selective electrodes for minimized contact resistance, exhibiting high brightness at relatively low drive voltage (3.5V). As one key step in wafer level packaging, the wafer bonding process was characterized with Moiré patterning to understand the temperature-dependent warpage profile, with simulation performed in guidance to final solution for compensating the warpage profile along the bonding process and afterwards. Different approaches were applied in learning the most effective bonding technique for this packaging structure. Further development is ongoing to improve the overall power efficiency and color quality, including optimal materials for ohmic contacts at both electrodes, large-area light extraction structure, and integrated phosphor material. This wafer-level packaging technology is scalable to large wafer size for achieving superior thermal and optical performance at high-throughput and low cost.

Thermal Analysis of xFD DRAM Packages Through Simulation and Experimental Validation

The design optimization for thermal management of systems relies heavily on accurate thermal models of the individual components. Invensas is developing new packaging concepts that provide enhanced and reliable performance electrically, thermally and mechanically. These development efforts use predictive finite element analysis to drive the optimization of package design for improved thermo-mechanical strain and thermal management. Therefore, it is important to validate such models through rigorous experimental thermal measurements. This work represents the 2nd half of our effort in the area of multi-die face-down stack thermal analysis. As was presented last year for the dual die face-down stack analysis, we will present details of our quad die face-down package design, assembly and the thermal test protocols. We will outline our methodologies for measuring thermal performance and achieving tight tolerances in the experimental apparatus as well as guidelines for making appropriate assumptions for associa...

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. ...

Assembly and Application Specific Methodology to Determine Accelerated Temperature Cycling Requirements for Pb-free Solder Joint Reliability

An assembly-and application-specific methodology is proposed to address the issue of accelerated temperature cycling test requirements for solder joint reliability. This is accomplished by first determining the amount of solder damage that is expected to accumulate in the field over a specified period of time from power cycles (both on/off cycles and mini cycles), and then designing ATC tests to generate the equivalent amount of damage. By equating the damage from the field to that from the tests, the number of ATC cycles can be determined. A step by step procedure is provided to guide the designer in the initial concept stage to design for reliability. An example is provided to highlight the differences between the proposed methodology and traditional correlation models.

Effects of A Rotated Chip Package on Mechanical and Thermal Performances

In the industry, heatsinks have commonly been oriented on IC packages so that their plan outlines are edge-wise parallel to those of the package. However there are situations where a rotated orientation is preferable, wherein the plan outline of the package is not ‘aligned’ with that of the heatsink assembly — in other words a situation where the heatsink location/orientation remain unchanged while the package itself is rotated in-plane. Mechanical design considerations may drive the need for such a non-traditional orientation, since the rotated package is anticipated to have lower mechanical stress levels in the silicon than the non-rotated one under the same heatsink-induced clamping load. In this study we examine the impact of such package rotation(s) on both the junction temperature performance of CPU packages and the package-level clamp-load induced mechanical stresses. Results show that the stress reduction in the rotated package is in the range of 15% to 60%. The thermal analysis also demonstrates that the effects on the hot spot temperature with 45 degrees rotation is an increase of almost 2°C compared with the non-rotated die case. This increase in junction temperature is expected to be even higher with lower airflow as seen in typical computer systems. Thus it may be inferred that it is important to consider the effects of die rotation on package performances.Copyright