Ruth A. Brain

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, <; 65mV/dec subthreshold slope and <;40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum2 cell size, containing >1.9 billion transistors.

Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.

Interconnect scaling: Challenges and opportunities

Transistor and interconnect pitch scaling has been used successfully for greater than 40 years to drive significant density and performance benefits in integrated circuits. Transistor performance has continued to improve due to pitch scaling combined with other process enhancements. Interconnects represent a much larger portion of the overall delay and cost of integrated circuits today than in the past. This paper reviews the relative comparison of interconnect and transistor scaling and key interconnect scaling challenges, and it highlights the transistor/interconnect co-optimization that is needed to create high performance and high yielding interconnects sufficient for todays ultra-large scale integration (ULSI) needs, and reviews future trends.

Integration of a 3-D capacitor into a logic interconnect stack for high performance embedded DRAM SoC technology

A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 μm2 DRAM cell capable of meeting >100μs retention at 95°C. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1-4]. We review the interconnect choices to enable the implementation of a high-aspect ratio 3-D capacitor into a SoC interconnect stack. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro in a 1Gbit eDRAM testchip [5].