S. Locorotondo

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

On the scalability of source/drain current enhancement in thin film sSOI

This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technology—excellent conformality and within wafer uniformity, no loading effect—overcome the limitations in this domain of the standard PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP) integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.

Demonstration of scaled 0.099µm 2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

We demonstrate electrically functional 0.099µm² 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L<inf>g</inf>∼40nm, 12–17nm wide Fins, and cell β ratio ∼1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM≫10%V<inf>DD</inf> down to 0.4V, and healthy electrical characteristics for the cell transistors [SS∼80mV/dec, DIBL∼50–80mV/V, and |V<inf>Tlin</inf>|≤0.2V (PMOS), V<inf>Tlin</inf>∼0.36V (NMOS)] are reported.

Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs

A P-SiC (Phosphorus doped Si1-xCx) SD (Source Drain) was developed on bulk-Si based nMOS FinFETs (n-FinFETs). P-SiC epitaxial growth on SD provides strain to boost n-FinFET mobility and drive current. Combination of LA (Laser Anneal) and low temperature RTA recovers P-SiC and PSi (Phosphorus doped Si, Si1-xPx) strain. A SiGe clad channel on pMOS FinFETs (p-FinFETs) was investigated. Narrower Si fin and SiGe epitaxial growth on fins increase mobility and drive current, which is based on the same carrier transport mechanism as conventional phonon scattering without velocity overshoot around 14nm node.

Integration challenges for multi-gate devices

The FinFET transistor is the most widely studied and known multi-gate architecture that has the potential to be scaled to beyond the 45 nm technology node. In this paper a number of integration issues have been addressed. In first section the patterning challenges have been discussed. Due to the particular layout of the FinFET devices a variation in fin width is seen due to the rounding of the fin opening. This problem can be addressed by looking at alternative litho settings and OPC. Next to that topography plays an important in patterning the gate. It is seen that the optimization of the different OE times is key in achieving a controlled gate profile without poly residues. Techniques like poly etch-back can be used to alleviate the topography issues as much as possible. Threshold voltage tuning with implantation is extremely difficult for narrow fin devices. Workfunction tuning by either deposited metal gate or full silicidation is seen as a more viable solution. The extensions and deep source/drain areas need to be as conformal as possible in order to avoid the dominance of the top channel over the sidewalls. However, conventional implantation techniques are unsuitable and alternative implantation techniques need to be investigated. Next to that, when high density is needed, the fin spacing will limit the allowed tilt angle due to implant shadowing. The sidewall crystal orientation is different from that of the top channel and this will impact the mobility of holes and electrons in a different way. Rotation of the fins over 45 degrees, the use of strained layers and strained SiGe source/drain have been briefly discussed as possible solutions to tackle this problem. Finally, the impact of the fin width on R/sub SD/ has been shown. Elevated source/drain has been brought forward as a solution to this problem.

Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON

We report for the first time on the use of a Ni fully germano-silicide (FUGESI) as a metal gate in pFETs. Using HfSiON dielectrics and comparing to Ni FUSI devices, we demonstrate that the addition of Ge in poly-Si gate results in 1) Fermi-level unpinning with >200 mV increase in work function; 2) improved dielectrics integrity: such as decreased 1/f and generation-recombination noise, improved channel interface, reduced gate leakage, and superior NBTI characteristics. The above experimental observations are correlated to oxygen vacancies related defects in the HfSiON layer

Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

Short gate-length Pt full-silicidation (FUSI) (PtSi and Pt2 Si) pMOSFETs were fabricated for the first time using a self-aligned Pt-FUSI process, demonstrating scalability (with no linewidth effects) down to ~ 60-nm gate lengths. The electrical results are compared to the Ni-FUSI (NiSi and Ni31Si12) pMOSFET devices. A low threshold voltage les|-0.29 V| was obtained for the Pt2Si-FUSI pMOSFETs on SiON and HfSiON indicating that the Pt2Si FUSI does not suffer from the Fermi-level pinning or gate-dielectric-charge effects on the HfSiON

193nm immersion lithography for high-performance silicon photonic circuits

Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer. In this paper, we present key technology challenges faced when using optical lithography for silicon photonics and advantages of using the 193nm immersion lithography system. We report successful demonstration of a modified 28nm- STI-like patterning platform for silicon photonics in 300mm Silicon-On-Insulator wafer technology. By careful process design, within-wafer CD variation (1sigma) of <1% is achieved for both isolated (waveguides) and dense (grating) patterns in silicon. In addition to dimensional control, low sidewall roughness is a crucial to achieve low scattering loss in the waveguides. With this platform, optical propagation loss as low as ~0.7 dB/cm is achieved for high-confinement single mode waveguides (450x220nm). This is an improvement of >20 % from the best propagation loss reported for this cross-section fabricated using e-beam lithography. By using a single-mode low-confinement waveguide geometry the loss is further reduced to ~0.12 dB/cm. Secondly, we present improvement in within-device phase error in wavelength selective devices, a critical parameter which is a direct measure of line-width uniformity improvement due to the 193nm immersion system. In addition to these superior device performances, the platform opens scenarios for designing new device concepts using sub-wavelength features. By taking advantage of this, we demonstrate a cost-effective robust single-etch sub-wavelength structure based fiber-chip coupler with a coupling efficiency of 40 % and high-quality (1.1×105) factor wavelength filters. These demonstrations on the 193nm immersion lithography show superior performance both in terms of dimensional uniformity and device functionality compared to 248nm- or standard 193nmbased patterning in high-volume manufacture platform. Furthermore, using the wafer and patterning technology similar to advanced CMOS technology brings silicon photonics closer toward an integrated optical interconnect.

Influence of oxide hard mask on profiles of sub-100 nm Si and SiGe gates

Oxide hard mask was found to have a profound effect on sub-100 nm Si and SiGe gates profiles. The gates patterned with hard mask only (photoresist is stripped after hard mask patterning) exhibit considerable profile distortion. It has been found that the distortion is caused by the ions deflection due to the charge accumulation on the hard mask. The distortion can be avoided by using either a thinner (15 nm–20 nm) hard mask (that accumulates less charges) or by increasing the ion energy, using higher (above 150 W) bias power (ions impinging the surface with higher speed are less likely to be deflected).