S. Cheramy

Development and characterisation of a 3D technology including TSV and Cu pillars for high frequency applications

As 3D packaging technologies are becoming more and more present in packaging roadmap, applications with higher requirement are rising continuously. Today, one of the main applications requiring 3D technologies is dedicated to nomadic components, including mobile phones, due to their very high compacity and integration capabilities. Those components need to work at high frequency, typically up to 1 GHz. For these frequencies, the resistance and the capacitance of the interconnections have to be minimized, in order to decrease the signal delay. This is a real challenge for 3D integration and especially for post process through silicon vias. In the first part of the paper, a study and a simple model to determine the main parameters responsible for resistance and parasitic capacitance variation will be presented. Then, a technical focus will be done on the improvement of the TSV electrical performances, especially the decreasing of the TSV parasitic capacitance from 2.41 pF to 0.76 pF based on Plasma Enhanced Chemical Vapour Deposition (PECVD) process development. Finally, the integration of this new material on a technological test vehicle with electrical results will be presented and discussed.

Development and characterisation of high electrical performances TSV for 3D applications

Today, a new trend in wafer level packaging is to add more than one die in the same package and, sometimes, to use the third dimension in order to : • Decrease the form factor of the final system • Improve the thermal and electrical performances of the device • Decrease the cost of the final product In order to stack the heterogeneous components in the third dimension, TSV (Through Silicon Vias) is a very promising technology compare to wire bonding. In this paper, the technological bricks specifically developed for 3D integration demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer [1] [2]. This flow needed to develop specific wafer level packaging technologies such as: • Top chip & bottom chip interconnections • High aspect ratio TSV included into the bottom wafer • Backside interconnections for subsequent packaging step • Temporary bonding and debonding of bottom wafer [3] [4] • Top chip stacking on bottom wafer In the first part of the paper, the complete process flow will be presented. Then, a technical focus will be done on the specific steps developed for the improvement of the TSVs electrical performances. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed. The electrical results obtained on a technological test vehicle will be firtly presented. Those results include electrical continuity, pillars resistance, TSV resistance and capacitance and TSV insulation and current losses. Then, the electrical results obtained with the “high electrical performances” process on the functionnal demonstrator will be showed, including a specific focus on the TSV capacitance measurements.

Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.

3D integration technology for set-top box application

In this paper, the technological bricks specifically developed for 3D integration of a set top box demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer [1]. This flow needed to develop specific wafer level packaging technologies such as: • Top chip & bottom chip interconnections • High aspect ratio TSV included into the bottom wafer • Backside interconnections for subsequent packaging step • Temporary bonding and debonding of bottom wafer • Top chip stacking on bottom wafer The complete process flow will be presented. Then, a technical focus will be done on the backside interconnections step. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed.

Electrical and morphological assessment of via middle and backside process technology for 3D integration

This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance point of view.

Innovative wafer-level encapsulation & underfill material for silicon interposer application

This paper is dedicated to the full integration of a new silicone-based material for Molding-Underfilling (MUF) on silicon interposer wafers containing Through Silicon Vias (TSVs) and top dice. The developments were carried out in the frame of “silicon package” where the silicon interposer is either reported on P-BGA or directly assembled on board. After a materials screening with regard to warpage issue, “molding last” was studied with the selected material, including compatibility with temporary bonding debonding, bumping, sawing and report on organic substrate. A focus is made on void-less molding-underfilling process development and wafer level reliability evaluation of first level (die to wafer) interconnections and TSV subjected to thermal cycles. For this study, a molding-last approach using a dry-film lamination process has been chosen. 170μm thick dice have been assembled on 120μm thin silicon interposers having 60μm diameter TSV via-last and encapsulated with optimized wafer-level MUF process. Electrical performances of the 35μm high Cu pillars interconnections have been measured on the interposer backside thanks to TSVs and rerouting. While the daisy chains resistances remained in specifications after molding and pre-conditioning, some electrical failures appeared after 250 thermal cycles. Cross-sections have highlighted cracks in solder joints leading to the development of an improved version of the compound. Finally, a complete test vehicle with a molded-underfilled interposer reported on an organic substrate has been achieved.

3D integration demonstration of a wireless product with design partitioning

3D integration has now made a place in semiconductor landscape and is coming closer from implementation in manufacturing. Although process bricks are almost all available now, there are still several challenges to solve before it is introduced in standard flows. One of those which is not commonly addressed is to get final customers interest by showing him evaluations and results on real industrial applications. Heterogeneous integration and the possibility to partition different functions of a product in separate layers is one of the advantages of 3D integration. In this paper, product partitioning with TSV and 3D integration is demonstrated without inducing any impact on final product functionality and on early package level reliability tests.

Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack

TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at low frequencies and radiofrequencies are reported. Simulations are done using a software performing device and electromagnetic co-simulations. The model and simulations are validated by measurements. Simulations to study the sensitivity of the TSV structure to the layout show changes in the TSV-to-substrate coupling behavior.

Underfilling techniques comparison in 3D CtW stacking approach

Die stacking in 3D integration increasingly deals with smaller soldered joints on flip chips which have to meet reliability requirements especially thermal cycling, vibrations, shocks. Adding an underfill between stacked chips is a solution to improve the structural integrity of those joints. In this work, different underfilling techniques are compared in chip to wafer (CtW) approach: one capillary underfill (CUF) and three pre-applied underfills (PAUF) including one non conductive paste (NCP) and two wafer level underfills (WLUF). These underfilling solutions are assessed using a test vehicle including daisy chains for electrical tests. Preconditioning and temperature cycling tests were carried out to monitor reliability. CUF and NCP enable to get good interconnections electrical resistance after 500 cycles. On the other side, WLUF process currently appears to be harder to implement because of lack of reproducibility and polymer entrapment at the bonding interface, preventing a reliable electrical contact. Advantages and drawbacks of each underfilling processes are also discussed regarding for instance maturity, easiness of process, throughput, creeping risks, entrapment risks, fine pitch and fine gap compatibility. It is obvious that PAUF are inevitable for 3D high density involving gap between stacked chips. However, related process speed is still low for PAUF. Further work on products and processes is thus needed to get reliability performances and cost-effectiveness suitable with high volume manufacturing.

A

Future many cores, either for high performance computing or for embedded applications, are facing the power wall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, using through silicon via (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipation devoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, in terms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eight die layers.