S. Mouhoubi

Body-diode related losses in Shield-Plate FETs for SiP 12V-input DC/DC buck converters operating at high-frequency (4MHz)

The power losses in System-in-Package (SiP) 12V-input DC/DC buck converters with advanced 30V Shield-Plate FETs (SP-FETs) are assessed by experiment and simulation with special interest in the body-diode contribution. Unlike previous work, rise/fall times and on/off deadtimes are in the nanosecond range to provide high efficiency at high frequency operation (1-4MHz).

A high-speed silicon FET for efficient DC-DC power conversion

A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1-5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.

Solutions to improve flatness of Id-Vd curves of rugged nLDMOS

This work summarizes results of TCAD simulations aiming to reduce/suppress the bump in the output characteristics of rugged nLDMOS devices. It is shown that the origin of the bump is not due to bipolar activation. Thus, by simple variations of the geometrical parameters and/or process variations, the intrinsic MOS of the nLDMOS could be driven in a regime allowing a drastic improvement of its Id-Vd flatness with limited impact on the sRon-Vbd trade-off.

Accumulation region length impact on 0.18µm CMOS fully-compatible lateral power MOSFETs with Shallow Trench Isolation

N-type lateral power MOSFETs (nLDMOS) with Shallow Trench Isolation (STI) and voltage capability between 12 and 22V are analyzed in this work by experiment and TCAD simulation. A 0.18um CMOS technology is used to integrate nLDMOS devices without additional mask or process. Differently from previous works, the paramount impact of the accumulation region length (Lacc) on the Safe Operating Area (SOA), gate-to-drain charge (Qgd) and Hot Carrier (HC) degradation is deeply explored to optimize the device electrical performance and reliability.

Near-zero gate bouncing in high-frequency converters with shield-plate FETs

The gate bouncing of the Shield-Plate FETs (SP-FETs) in synchronous buck converters is investigated in this work for the first time. A comparative analysis between a 30V SP-FET and a 30V TP-FET (Trench Power MOSFET) working as a synchronous switch is provided by experimental results and mixed-mode simulation. Although the current conduction during the deadtime is due to different mechanisms, the extremely low Crss/Ciss ratio (<; 0.01) is identified as the main responsible for the negligible gate bouncing in SP-FETs. The gate bouncing immunity is presented as a new paradigm for the circuit/device co-design, thus allowing the reduction of the driver deadtime and the MOSFET threshold voltage in order to achieve efficiency peaks above 90% for 12V-to-1.2V conversion at 1MHz operation frequency.

Improved Trench-Based Power Rectifiers for High-Temperature Smart-Power Applications

Trench-based power rectifiers with optimized electrical performance are presented in this letter in order to cover high-temperature applications and high-voltage capabilities ranging from 70 to 100 V. A three-step epitaxial layer substantially improves forward, reverse, and dynamic recovery characteristics up to 200degC, exhibiting considerable advantages over conventional planar rectifiers.

A family of robust DMOS devices for automotive applications

This paper presents different methodologies to optimize devices of smart power technologies for robustness consideration. A split gate concept is used to improve the flatness of Id-Vd curves of the nVDMOS by maintaining the Intrinsic MOS in a stable operating regime. The split gate is also used to increase the BVdss of the pLDMOS. An additional buffer at the end of the drift region of the nLDMOS helps extending the SOA limits due to a controlled positive differential resistor branch.

Gate-Oxide Breakage Assisted by HCI in Advanced STI DeMOS Transistors

This letter provides, for the first time, experimental evidence supporting that hot-carrier injection not only degrades electrical performance in drain-extended MOS transistors with shallow trench isolation (STI DeMOS) but also induces a severe gate-oxide (Gox) degradation and wear-out of the oxide. During the Gox degradation at high-stress conditions, a steep increase of interface traps (Nit) and oxide traps (Not) is detected in the accumulation region by using charge pumping. A subsequent fast degradation of the device electrical characteristics is observed.

Improved current filament control during Zener diode zapping

Abstract The filament-based failure is investigated in this work by experiment and 3D TCAD simulations in Zener diodes used as one-time-programmable (OTP) memories. Different zapping mechanisms with their inherent electrical and physical signatures are identified and elucidated. Moreover, a new trenched Zener structure is fabricated and tested in order to provide static current filaments as well as to minimize the power to generate them.