B. Desoete

Thermal resistance assessment in multi-trenched power devices

Abstract For the first time the thermal resistance ( R th ) of Multi-Trenched (MT) power devices is evaluated and compared with their Deep Trench Isolation flanked (DTI-flanked) and bulk counterparts. The R th extraction is carried out by adapted test structures based on the four-point heater/sensor method. Additional TCAD simulation supports the experimental stationary values and proves that dynamic heating can limit the MT power devices energy capability.

Theoretical analysis of XtreMOS ™ power transistors

This work provides a new theoretical approach addressed to the XtreMOSTM and equivalent structures. An analytical sRonxBVdss model is provided to demonstrate the superior electrical performance of XtreMOSTM structure in the domain of the high power MOSFETs at medium voltage capability (50-200 V). Moreover, geometrical and technological parameters can be easily optimized by means of simple expressions. In order to support and validate the theoretical approach, numerical simulation and experimental data are included.

Safe Operating Area Considerations for Integrated Trench-Based Power Devices

This paper discusses the hot-carrier and electrical safe operating area (SOA) of trench-based integrated power devices. The hot-carrier SOA is determined by the avalanche current, exhibiting a maximum at intermediate drain voltage. The initial hot-carrier degradation is dependent on the crystal plane on which the gate oxide is grown. During hot-carrier stress, interface states are formed in the devices accumulation region. No channel degradation is observed. The electrical SOA of the trench-based MOS (TB-MOS) is much larger than a comparable lateral DMOS (LDMOS) or vertical DMOS (VDMOS). Even for 100-ns pulses, the TB-MOS exhibits electrothermal effects, contrary to LDMOS and VDMOS. Finally, the intrinsic gate oxide quality of the trench gate oxide is reported on. It is proven that the oxide time-dependent dielectric breakdown is determined by the thinnest oxide along the trench sidewall.

Anomalous Bulk Current Effects in Trench-Based Integrated Power Transistors

This letter reports on anomalous bulk current effects in vertically integrated power transistors. The transistors use trench processing to make a vertical stack of gate oxide and drift oxide, the latter being used to completely deplete the drift region. The bulk current - a direct measure for the maximum impact ionization in the device - is shown to reach a maximum at intermediate drain voltage, and decreases for increasing drain voltage. The latter has important consequences for the hot carrier reliability evaluation of the transistors. A comparison between a standard lateral DMOS and a trench-based MOS is made.

Electro-thermal characterization and simulation of integrated multi-trenched XtreMOSTM power devices

This paper presents a new methodology to characterize and simulate the electro-thermal aspects of packaged power drivers using multi-trenched XtreMOS devices. Electrical device data is collected by pulsed and DC measurements. Thermal data is collected through on-chip sensors -and through a full surface high resolution transient interferometric mapping (TIM). For the first time a data driven segmented electro-thermal transient model is proposed to describe accurately the thermal profile behavior for the mutli-trenched devices. Further investigations of the thermal heating impact on the driver due to the low thermal conductivity of the trenches (SiO2) have been carried out.

Hot carrier effects in trench-based integrated power transistors

This paper reports for the first time on anomalous hot carrier effects observed in vertically integrated trench-based (TB-MOS) power transistors. The avalanche current reaches a maximum at intermediate drain voltage, and decreases for increasing drain voltage. The hot carrier lifetime of the transistors yields a minimum at intermediate drain voltage, and not at the maximum drain voltage. Charge pumping experiments enable to locate the degradation in the TB-MOS. A degradation model is proposed.

Improved Trench-Based Power Rectifiers for High-Temperature Smart-Power Applications

Trench-based power rectifiers with optimized electrical performance are presented in this letter in order to cover high-temperature applications and high-voltage capabilities ranging from 70 to 100 V. A three-step epitaxial layer substantially improves forward, reverse, and dynamic recovery characteristics up to 200degC, exhibiting considerable advantages over conventional planar rectifiers.

High-Voltage trenched rectifiers for Smart Power technology

High-voltage junction and Schottky trenched power rectifiers (HV-JTPR and STPR) are fabricated and analyzed in this paper for 70 V to 100 V reverse voltage applications. Resulting from their combination, an innovative hybrid device (HTPR), with alternated Schottky/Junction fingers, is a proper solution to control the trade-off between the losses in forward and reverse modes.

Optimisation of metal connections in lateral DMOS transistors for driving applications

This paper presents the optimisation of the routing of multi-finger current drivers, based on lateral DMOS transistors, for switching applications, in order to limit the metal contribution. to the total driver on-resistance. The metal2 collecting current from the device fingers out of the source and drain, is shown to be the major contributor to the added series resistance for all aspect ratios, as long as the number of metal2 tracks is large enough. The experimental characterisation of the metal connection influence on the device on-resistance is successfully supported by circuit simulations, based on a lumped resistor network model of the driver.

Experimental demonstration of a vertical LOCOS Insulated Base Transistor

In this paper we demonstrate, for the first time, electrical results of vertical LOCOS based Insulated Base Transistors (IBT) fabricated in a 85 V BiCMOS process. Experimental results show that the devices exhibit ‘transistor like’ characteristics and show enhancements with respect to saturation current level when compared to MOSFET equivalents. Furthermore, a cathode cell structure with a MOSFET in parallel to the IBT displays superior performance when compared to devices where this is eliminated.