Hans T. Heineken

Manufacturability analysis environment-MAPEX

A CAD manufacturability analysis environment, MAPEX, is described in this paper. It can be used to extract a large number of manufacturability/yield relevant design attributes from an IC layout. The extracted attributes can then be used to improve design tools/strategies or to analyze the reasons for observed yield loss.<<ETX>>

CAD at the design-manufacturing interface

Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the paperalong with some of its key procedures and algorithms. Illustrationsof MAPEX 2 applications and performance figures are provided as well.

Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs

A sound IC design methodology must be supported by adequate manufacturability assessment tools. These tools should assist a designer in predicting IC manufacturing cost in as early a design stage as possible. In this paper a yield model is proposed that takes as input a standard cell netlist and produces as output a yield estimate without performing placement and routing. This yield model has been successfully used to predict the interconnect yield of standard cell designs that were implemented with two place and route tools. The proposed yield model can be used as a crucial component in the objective function of a circuit synthesis tool as well as in technology mapping optimization.

Yield loss forecasting in the early phases of the VLSI design process

This paper describes three new yield models. The first takes as input the critical area of a layout; the second approximates the critical area with the minimum spacing area between metal lines; and the third uses transistor density to model critical area. The models were developed and verified using manufacturing data.

Manufacturability analysis of standard cell libraries

Time-to-market and resource limitations typically drive fabless design houses to invest in commercial standard cell libraries. Selecting the appropriate library, however, is nontrivial, and is made harder when only a few select cells are provided for analysis. In this paper a methodology is presented to efficiently compare multiple cell libraries from a manufacturability perspective. In addition, an application is presented that indicates the effort required to build an internal library may be well warranted for high volume designs.

Standard cell interconnect length prediction from structural circuit attributes

A new interconnect model is proposed that predicts the distribution parameters of net lengths. The model takes as input a standard cell netlist and provides as output estimates of the mean and variance offer length on a net by net basis. The model was developed and verified on designs produced with two different place and route algorithms.

Maximizing wafer productivity through layout optimizations

Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and has been shown to lower die cost by 4.6%. This paper applies DFM to the routing. In particular this paper analyzes the effects of various routing options on wafer productivity and shows that if properly applied DFM can lead to a further die cost reduction of 9%.

Performance - manufacturability tradeoffs in IC design

Traditional VLSI design objectives are to minimize time-to-first-silicon while maximizing performance. Such objectives lead to designs which are not optimum from a manufacturability perspective. The objective of this paper is to illustrate the above claim by performing performance/manufacturability tradeoff analysis. The basis for such an analysis, in which the relationship between a products clock frequency and wafer productivity is modeled, is described in detail. New applied yield models are discussed as well.

Manufacturability and testability oriented synthesis

This paper presents a case for new generation synthesis tools that incorporate manufacturability and testability as optimization factors in addition to traditional factors such as timing, die-area, and power. A suitable approach for manufacturability oriented synthesis is the interconnect field model, which estimates yield as a function of netlist attributes. Testability oriented synthesis encompasses various design-for-test (DFT), synthesis for testability, (SFT) and the high-level test synthesis (HLTS) techniques during the synthesis process.

Cost trade-offs in system on chip designs

Advances in technology have led to a drive towards system on chip (SoC) designs. However manufacturing and test costs have increased as rapidly as design complexity. Hence, in order to produce SoC designs at reasonable cost, both system-level and die-level cost trade-offs must be made. This paper illustrates the methodologies used in analyzing such trade-offs. Examples in the paper indicate that using advanced technologies to manufacture SoC designs may sometimes be detrimental in terms of total system costs.