Jitendra Khare

Yield-oriented computer-aided defect diagnosis

Any good yield-oriented defect strategy must have two main components-(a) the ability to perform rapid defect diagnosis for yield learning, and (b) the ability to efficiently extract defect parameters from the manufacturing line. In this work, an inductive fault analysis (IFA)-based defect methodology is investigated to see if it meets the above requirements. Using an SRAM test vehicle as an example, the research analyzes whether computer-generated mappings between defect types and tester fail data can provide sufficient resolution for both, defect diagnosis and defect parameter characterization. >

Extraction of defect size distributions in an IC layer using test structure data

This paper demonstrates the need for specialized test structures and algorithms to obtain defect characteristics which are necessary for accurate yield prediction. Using one such specialized test structure, a general methodology for extracting size distribution parameters for both shorts and opens in any IC layer, which is independent of defect and yield models, is developed in this paper. The application of this methodology is illustrated by means of a fabrication experiment. >

Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cells critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32*32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method. >

Inductive contamination analysis (ICA) with SRAM application

This paper proposes a new simulation-based fault modeling methodology. The methodology-an extension of Inductive Fault Analysis-uses the contamination-defect-fault simulator CODEF to directly relate effects of process-induced contamination to circuit-level malfunctions. The application of this methodology (called Inductive Contamination Analysis) is demonstrated by development of SRAM fault models.

CAD at the design-manufacturing interface

Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the paperalong with some of its key procedures and algorithms. Illustrationsof MAPEX 2 applications and performance figures are provided as well.

From Contamination to Defects, Faults and Yield Loss

Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.

Enabling embedded memory diagnosis via test response compression

This paper introduces a method that enables failure diagnosis of BISTed memories by compression of test responses. This method has been tested by simulation of memories with various specifications, fail patterns and test algorithms. The proposed method has been implemented in 0.18 /spl mu/ CMOS IC.

Fault characterization of standard cell libraries using inductive contamination analysis (ICA)

In this paper we demonstrate an Inductive Contamination Analysis (ICA)-based methodology for complete fault characterization of standard cell libraries. Such a characterization has applications in accurate assessment of defect coverage, contamination diagnosis, gate-level delay characterization and test generation.

Yield loss forecasting in the early phases of the VLSI design process

This paper describes three new yield models. The first takes as input the critical area of a layout; the second approximates the critical area with the minimum spacing area between metal lines; and the third uses transistor density to model critical area. The models were developed and verified using manufacturing data.

SRAM-based extraction of defect characteristics

In modern IC manufacturing, extraction of defect characteristics for yield estimation is of prime importance. Test structure based defect characterization procedures suffer from two drawbacks-wastage of silicon area and short-loop mode of operation. This paper presents a SRAM-based characterization methodology, which can eliminate both the above drawbacks. The application of this methodology is also illustrated by means of an industrial experiment, which indicates that the procedure can be applied to all defect types for which the SRAM monitor has a high resolution of diagnosis.<<ETX>>