Sam Chang

Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.

Design and characterization of a 12.8GB/s low power differential memory system for mobile applications

This paper describes the design and characterization of a low power differential memory interface targeted for mobile applications. The initial design of the memory interface achieves 2.7 to 4.3GB/s data bandwidth and consumes 3.3mW/Gb/s at 4.3GB/s operation. The design allows two x16 stacked dies to be fit into a 12mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is reviewed and its performance is analyzed. We demonstrate that, compared to LPDDR2 memory interface based on single-ended signaling, the differential memory interface overcomes most of channel related issues such as crosstalk and SSO noise and provides a very clean channel response. Thus, the resulting extra system margin can be used to compensate for extra timing jitter and system noise, enabling lower power and lower system cost. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the memory system performance and to validate the memory statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.

Jitter Amplification Considerations for PCB Clock Channel Design

Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.

Prediction of System Performance Based on Component Jitter and Noise Budgets

Conventional ways of summing component specifications to balance voltage and timing budgets are increasingly problematic as data rates continue to scale higher for high speed links. For instance, performance degradation caused by transmitter jitter is more severe than that caused by receiver jitter due to jitter coloring by the passive channel. Furthermore, certain jitter components could interact in the system so it is inaccurate to treat them as independent variables. A system voltage and timing budgeting process hence requires a sophisticated method to accurately predict the overall system performance based on the component specifications. With the recent introduction of a statistical CAD tool, the impact of each individual component, including both deterministic and random jitter, can be co-simulated [l]-[3]. This paper demonstrates the usage of this statistical CAD tool for modeling component budgets. We verify the accuracy of our modeling approach by correlating with a FlexIOreg parallel link interface. Then, we apply the proposed methodology to a PCI Expressreg bus system to estimate the system performance based on published component jitter specification.

In-situ characterization of 3D package systems with on-chip measurements

Characterization of I/O channels in 3D package systems is quite challenging as it is difficult to observe signal quality. A traditional way of measuring each device in a component level does not capture complex interaction in 3D integration. Although a sense line can be designed to externally measure noise on power lines, it is not feasible for signal lines as it significantly alters the signal quality. Hence, on-chip measurement features are highly desirable for 3D package systems including emerging Through-Silicon Vias (TSV) technology. In this paper, four key on-chip measurement concepts and circuitries are reviewed: eScope for measuring overall link margins, eWave for capturing a signal waveform, nScope for generating and monitoring on-chip power noise, and zScope for measuring power distribution network (PDN). These circuitries are implemented in a low power differential memory interface. The test vehicle is built based on Package-on-Package (PoP) environment. Measurements from the test vehicle are compared with the predicted data based on simulation.

Hybrid Statistical Link Simulation Technique

Accurate analysis of link performance including deterministic and random effects as well as advanced signal conditioning schemes is crucial in modern high-speed I/O design. In recent years, statistical link performance tools such as LinkLab and StatEye are introduced to efficiently analyze the overall link performance with both deterministic and random noise. The statistical-domain analysis has limitations in terms of its capability of accurately simulating system nonlinearity, jitter, as well as coding. In this paper, we present a new hybrid approach that combines statistical and time-domain techniques to efficiently overcome these limitations. The proposed method has several key contributions: 1) capture system nonlinearity; 2) separately simulate short-term deterministic jitter in the time domain and long-term deterministic and random jitter in the statistical domain; 3) co-simulate clock and data channels to capture jitter tracking; and 4) co-simulate signal and power integrity to include simultaneous switching output noise. We demonstrate this hybrid approach by studying the jitter tracking capability of a clock forwarding scheme and the effectiveness of coding in terms of system bit error rate.

Statistical link analysis of high-speed memory I/O interfaces during simultaneous switching events

Single-ended signaling systems, popular in memory I/O interfaces, are limited by signal and power integrity issues such as crosstalk and simultaneous switching output noise (SSO). At high data rates, the single-ended systems also suffers from random noise and timing jitter. In this paper, we present an integrated signal and power integrity simulation flow that combines statistical and transient simulation methods to enable the characterization of single-ended systems to account for random timing jitter in addition to the traditional SI issues focused on the deterministic noise such as intersymbol interference (ISI), crosstalk, and SSO noise. To include SSO noise, we co-simulate power distribution network (PDN) and channel models and treat SSO noise as another form of crosstalk. To capture any system nonlinearity, we employ time-domain based multi-edge response (MER) method to characterize the deterministic and passive portion of channels. Then, random noise and timing jitter impact are included via statistical approach. We use GDDR system to demonstrate our simulation flow.

Clock jitter modeling in statistical link simulation

Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate prediction with device jitter and noise. Currently available statistical analysis techniques focus on modeling of data channels and the impact of a clock channel is often ignored or primitively approximated using a simple receiver sampling distribution. Thus, it ignores any jitter tracking between data and clock signals. In this paper, a general formulation is presented to model the common jitter source between data and clock signals in order to capture any jitter tracking between them. To demonstrate the usage of the proposed formulation, we have derived various models for commonly used clocking architectures, such as the forwarded clocking scheme in XDR™, DDR, and GDDR systems and the common source RefClk architecture used in PCIe channels. The formulation is verified numerically by using an internally developed CAD tool.

Accurate System Voltage and Timing Margin Simulation in CDR Based High Speed Designs

Accurate analysis of system timing and voltage margin at a target bit error rate across process, voltage, and temperature variations is required for high volume production of high speed systems. This in turn requires a statistical simulation framework to model the effectiveness of advanced signaling techniques such as transmitter equalization and receiver decision feedback. Furthermore, for data and telecommunication networking serial links, one must also carefully model the clock-data recovery circuits (CDR) and understand their impact on system voltage and timing margin. In this paper, we first present a stochastic simulation framework and describe a modeling methodology for CDR circuits. We then compare the simulation results based on CDR modeling to a simple method, which uses a quadrature sampling based timing recovery model. Finally, we correlate the simulation results to lab measurements to validate the proposed approach

Statistical link analysis and in-situ characterization of high-speed memory bus in 3D package systems

High-speed link design in a 3D package system poses unique challenges due to the fact that it provides limited visibility to signal quality and that supply noise induced jitter is large due to a poor power distribution network in a small form factor. This paper outlines a statistical link simulation flow to accurately capture the impact of timing jitter due to power supply noise in 3D systems. The analysis includes on-chip jitter accumulation and link-level jitter tracking by considering both passive channel and on-chip signal path. On-chip measurement techniques which allow in-situ testing of the overall link margin are also described.