Saman Kiamehr

NBTI mitigation by optimized NOP assignment and insertion

Negative Bias Temperature Instability (NBTI) is a major source of transistor aging in scaled CMOS, resulting in slower devices and shorter lifetime. NBTI is strongly dependent on the input vector. Moreover, a considerable fraction of execution time of an application is spent to execute NOP (No Operation) instructions. Based on these observations, we present a novel NOP assignment to minimize NBTI effect, i.e. maximum NBTI relaxation, on the processors. Our analysis shows that NBTI degradation is more impacted by the source operands rather than instruction opcodes. Given this, we obtain the instruction, along with the operands, with minimal NBTI degradation, to be used as NOP. We also proposed two methods, software-based and hardware-based, to replace the original NOP with this maximum aging reduction NOP. Experimental results based on SPEC2000 applications running on a MIPS processor show that this method can extend the lifetime by 37% in average while the overhead is negligible.

Aging-aware logic synthesis

As CMOS technology scales down into the nanometer regime, designers have to add pessimistic timing margins to the circuit as guardbands to avoid timing violations due to various reliability effects, in particular accelerated transistor aging. Since aging is workload-dependent, the aging rates of different paths are non-uniform, and hence, design time delay-balanced circuits become significantly unbalanced after some operational time. In this paper, an aging-aware logic synthesis approach is proposed to increase circuit lifetime with respect to a specific guardband. Our main objective is to optimize the design timing with respect to post-aging delay in a way that all paths reach the assigned guardband at the same time. In this regard, in an iterative process, after computing the post-aging delays, the lifetime is improved by putting tighter timing constraints on paths with higher aging rate and looser constraints on paths which have less post-aging delay than the desired guarband. The experimental results shows that the proposed approach improves circuit lifetime in average by more than 3X with negligible impact on area. Our approach is implemented on top of a commercial synthesis toolchain, and hence scales very well.

Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach

Transistor aging is a major reliability concern for nanoscale CMOS technology that can significantly reduce the operation lifetime of very large-scale integration chips. Negative bias temperature instability (NBTI) is a major contributor to transistor aging that affects pMOS transistors. On the other hand, leakage power is becoming a dominant factor of the total power with successive technology scaling. Since the input combinations applied to a logic core have a significant impact on both NBTI and leakage power, input vector control can be used to optimize both phenomena during idle cycles. In this paper, we present an efficient input vector selection technique based on linear programming for cooptimizing the NBTI-induced delay degradation and leakage power consumption during standby mode. Since the NBTI-induced delay degradation and leakage power are not affected by the input vector in the same direction, we provide a pareto curve based on both phenomena. A suitable point from such a pareto curve is chosen based on circuit conditions and requirements during runtime.

Aging-aware timing analysis considering combined effects of NBTI and PBTI

Transistor aging due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) is one of the major reliability issues of VLSI circuits fabricated at nanometer technology nodes. Transistor aging increases the circuit delay over the time and ultimately leads to lifetime reduction of VLSI chips. Accurate aging-aware timing analysis is a key requirement to consider these effects in the design cycle. Our analysis shows that a separate (independent) analysis of different sources of aging leads to significant overestimation of post-aging delay. To overcome the problem of existing methods, we propose a new aging-aware gate delay model that precisely captures the combined effect of different aging sources on delay. Our results obtained from a set of benchmark circuits show that, our proposed gate-delay model estimates the aging-induced Δdelay by 7.8% (translating to 36.0% MTTF) more accurately in comparison to prior techniques. Moreover, we present a flow for integrating the proposed gate delay model with commercial timing analysis tools.

A linear programming approach for minimum NBTI vector selection

Transistor aging is a serious reliability challenge for nanoscale CMOS technology which can significantly reduce the operation lifetime of VLSI chips. Negative Bias Temperature Instability (NBTI) is the major contributor to transistor aging which affect PMOS transistors. The input vectors applied to the logic core has a significant impact on the overall aging of the logic block. In this paper, we present an efficient input vector selection technique based on Linear Programming (LP) to be used for maximum relaxation during the standby phase. We consider an accurate delay model for post-aging critical paths. Our mixed-LP (binary-relaxed) formulation scales well for very large circuits and provides near-optimal solutions. Experimental results and comparison with Monte-Carlo simulations show the speedup (4-5 orders of magnitude) and further optimization (11%) of our approach. Using these input vectors for the standby phase, the aging effect can be postponed by 71% in average.

Incorporating the impacts of workload-dependent runtime variations into timing analysis

In the nanometer era, runtime variations due to workload dependent voltage and temperature variations as well as transistor aging introduce remarkable uncertainty and unpredictability to nanoscale VLSI designs. Consideration of short-term and long-term workload-dependent runtime variations at design time and the interdependence of various parameters remain as major challenges. Here, we propose a static timing analysis framework to accurately capture the combined effects of various workload-dependent runtime variations happening at different time scales, making the link between system-level runtime effects and circuit-level design. The proposed framework is fully integrated with existing commercial EDA toolset, making it scalable for very large designs. We observe that for benchmark circuits, treating each aspect independently and ignoring their intrinsic interactions is optimistic and results in considerable underestimation of timing margin.

Statistical analysis of BTI in the presence of process-induced voltage and temperature variations

In nano-scale regime, there are various sources of uncertainty and unpredictability of VLSI designs such as transistor aging mainly due to Bias Temperature Instability (BTI) as well as Process-Voltage-Temperature (PVT) variations. BTI exponentially varies by temperature and the actual supply voltage seen by the transistors within the chip which are functions of leakage power. Leakage power is strongly impacted by PVT and BTI which in turn results in thermal-voltage variations. Hence, neglecting one or some of these aspects can lead to a considerable inaccuracy in the estimated BTI-induced delay degradation. However, a holistic approach to tackle all these issues and their interdependence is missing. In this paper, we develop an analytical model to predict the probability density function and covariance of temperatures and voltage droops of a die in the presence of the BTI and process variation. Based on this model, we propose a statistical method that characterizes the life-time of the circuit affected by BTI in the presence of process-induced temperature-voltage variations. We observe that for benchmark circuits, treating each aspect independently and ignoring their intrinsic interactions results in 16% over-design, translating to unnecessary yield and performance loss.

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions

Transistor aging due to Negative Bias Temperature Instability (NBTI) is a major reliability challenge for embedded microprocessors at nanoscale. It leads to increasing path delays and eventually more failures during runtime. In this paper, we propose a novel microarchitectural approach combining aging-aware instruction scheduling with specialized functional units to alleviate the impact of NBTI-induced wearout. To achieve this, the instructions are classified depending on their worst-case delay into critical (i.e. the instructions whose delay is close to the cycle boundary) and non-critical instructions (i.e. those instruction with larger timing slack). Each of these classes uses its own (specialized) functional unit(s). By that means it is possible to increase the idle ratio of the units executing the critical instructions, which can be used to extend lifetime by up to 2.3x in average compared to the usually used balanced scheduling policy.

Investigation of NBTI and PBTI induced aging in different LUT implementations

Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. These phenomena can shift the threshold voltage of transistor over time, increase their delays and cause timing failure and ultimately reduction of lifetime of VLSI chips. As much as FPGAs benefit from the most scaled and advanced technologies, they become susceptible to transistor aging. In this paper, we investigate the effect of transistor aging, due to NBTI and PBTI, in look-up tables (LUTs), by considering different implementations through detailed SPICE simulations. We found out that the delay degradation due to transistor aging depends on the mapped configuration, usage (input signal probability) as well as the specific LUT implementation. Moreover, the specific configuration mapped previously into an LUT has a considerable effect on the delay degradation of the currently used configuration of that LUT. We also found that the all-zero configuration which is normally used as the standby configuration is not the best choice and it may even result in high delay degradation.

Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates

As CMOS feature size scales to the nanometer regime, transistor aging mostly due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), has emerged as a major reliability concern. Threshold voltage shift causes the circuit to fail, once the post-aging delay exceeds the timing constraint. In this paper, we investigate the stacking effect of transistors on aging and propose a novel input/transistor reordering approach to alleviate the effect of NBTI and HCI during the active mode operation of the circuit. According to the results, the circuit failing due to aging effect is postponed by increasing the operational lifetime for ISCAS benchmarks by 23.6%, in average, while it has a negligible effect on delay, area, and power compared to the original cell input ordering.