Samuel Suhard

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).

Integration of the ZoneBOND™ temporary bonding material in backside processing for 3D applications

Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. A key step in this process is the bonding of the device wafer to a carrier wafer prior to wafer thinning, by using a temporary adhesive layer. While great progress has been made over the past 2 years with respect to the wafer-support system, some of these materials including thermoplastics, laser-degradable or chemically dissolvable materials can present some integration limitations, especially if low-melting-point solders or high-topography structures are present on the backside of the wafers. The approach pursued by imec was for the first time demonstrated on full CMOS wafers using the BSI HT-10.10 thermoplastic material in a 300mm production line, and this work furthers the previous development by successfully demonstrating the integration of the room temperature peelable ZoneBOND temporary bonding material from Brewer Science as a one-to-one alternative to the BSI HT-10.10 material.

Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora® LK HM

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.

Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down

Among the technological developments pushed by the emergence of 3D-ICs, wafer thinning has become a key element in device processing over the past years. As volume increases, defects in the overall thinning process flow will become a major element of focus in the future. Indeed product wafers arriving at this point of process are of maximum value. Fundamental understanding of the potential defects and their impact on devices is therefore needed to minimize their recurrence.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I_OFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (W_NW≤25nm, H_NW~22nm), with increased doping enabling ION improvement without I_OFF penalty for W_NW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. V_T mismatch performance shows higher A_VT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (d_NW≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low I_OFF, I_G, and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.

Challenges and novel approaches for photo resist removal and post-etch residue removal for 22 nm interconnects

The critical challenges of removal of post metal hard mask etch photo resist removal and post low-k etch residue removal are described. An overview of some new non-plasma based approaches is presented.

3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers

The fabrication of small pitch micro-bumps on thinned wafers after through silicon vias (TSV) reveal and back side passivation is reported. Device wafers are bonded on temporary silicon carrier using the novel ZoneBONDTM material. Micro-bump scaling involves a reduction of the overall solder volume. These structures are now reaching such dimensions that solder diffusion becomes problematic. One key advantage of the ZoneBONDTM material is to enable room temperature debonding process in case of solder bumps and therefore prevent any metal diffusion or solder consumption prior to stacking. The glue compatibility with the micro-bumping module and the challenges to perform these processes on the back side of device wafers are reported in this study. The main process steps studied are the lithography and its alignment accuracy as well as the electro chemical deposition of the micro-bumps.

3D stacking cobalt and nickel microbumps and kinetics of corresponding IMCs at low temperatures

To improve the performance of 3D electronic chips, dense I/O and interconnects are required. Increasing the density of interconnects requires smaller pitch micro-bumps. However, when scaling down microbumps several challenges have to be taken into account. Lithography of dense and high aspect ratio bump, wet etching of seed and barrier layer, solder volume and intermetallics (IMC) formation are some of the challenges that needs to be addressed. With reducing bump dimensions, solder volume decreases as well, converting Sn to complete IMC during the Thermo-Compression-Bonding (TCB) process. Full IMC formation increases stress in the joint, leading to crack formation and a brittle connection. Beside concerns about the IMC layer, the UBM (under bump metallization) consumption by the solder has to be addressed as well. Therefore, it is important to select the right UBM and solder to have enough Sn and UBM left in the joint for the time the product is working at a specific temperature [1].

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental ...

Development of a wet silicon removal process for Replacement Metal Gate and Sacrificial Fin.

Samuel Suhard, Farid Sebaai, Antoine Pacco, Anabela Veloso, Laureen Carbonell, Martine Claes, Herbert Struyf, Paul Mertens and Stefan De Gendt 1 IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium 2 Dept.of Chemistry, KULeuven, Celestijnenlaan 200F, B-3001 Leuven, Belgium Introduction The recent development of high k /metal gate has led to the continuity of device scaling and Moore’s law. The Gate last approach (Replacement Metal Gate (RMG)) has been investigated extensively since it enables a broad choice of material to be used, and hence yielding affording better electrical performance [1]. From a wet development point of view, the key step in the RMG approach (figure 1) is the dummy polysilicon removal since it is crucial that no residues remain. This paper will focus first on developing a stable and reproducible process for wet polysilicon removal on 300 mm wafers and secondly on transferring the wet removal process to similar dummy silicon approaches: SiGe RMG and Sacrificial Fin (Sac-Fin). The latter can be seen as a simplified RMG flow (Figure 4).