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Dive into the research topics where Richard J. Harries is active.

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Featured researches published by Richard J. Harries.


electronic components and technology conference | 2013

A preliminary solder joint life prediction model by experiment and simulation for translation of use condition to temperature cycling test condition

Ru Han; Min Pei; Alan Lucero; Daeil Kwon; Yun Ge; Richard J. Harries; Pardeep K. Bhatti; Tieyu Zheng

This paper introduces a new preliminary solder joint fatigue model based on thermo-mechanical finite element analysis (FEA) simulation results and the use of extensive solder joint reliability (SJR) experimental data for ball grid array (BGA) packages. A comprehensive FEA modeling method for temperature cycling (TC) loading was defined based on thorough and detailed convergence studies on modeling approaches, mesh sensitivities, analysis parameters, material parameters, boundary conditions and thermal loading conditions. Extensive reliability data was collected for various package designs, form factors, board thicknesses and testing conditions to demonstrate feasibility. The result is a solder joint fatigue model derived from FEA thermal mechanical modeling results and empirical reliability data regression fitting. Next, this FEA modeling method was coupled with a transient heat transfer method to integrate thermal gradients that exist in actual product use condition (UC) duty cycles. A new UC method is demonstrated based on a common physical damage metric calculated from numerical simulations for UC (with real user behavior data and temperature gradient) and TC (uniform temperature) conditions. The derived SJR fatigue model was combined with the newly developed UC method to establish new TC test requirements based on the actual use condition duty cycling.


Archive | 2003

Mold compound cap in a flip chip multi-matrix array package and process of making same

Vassoudevane Lebonheur; Richard J. Harries


Archive | 2011

THERMAL EXPANSION COMPENSATORS FOR CONTROLLING MICROELECTRONIC PACKAGE WARPAGE

Pramod Malatkar; Richard J. Harries


Archive | 2006

Compliant structure for an electronic device, method of manufacturing same, and system containing same

Sudarshan Rangaraj; Shankar Ganapathysubramanian; Richard J. Harries; Mitul Modi; Sankara J. Subramanian


Archive | 2006

Embedded capacitors for reducing package cracking

Mitul Modi; Sudarshan Rangaraj; Shankar Ganapathysubramanian; Richard J. Harries; Sankara J. Subramanian


Archive | 2006

Microelectronic assembly having a periphery seal around a thermal interface material

Mitul Modi; Sudarshan Rangaraj; Shankar Ganapathysubramanian; Richard J. Harries; Sankara J. Subramanian


Archive | 2012

Apparatuses and methods to enhance passivation and ILD reliability

Richard J. Harries; Sudarashan V. Rangaraj; Bob Sankman


Archive | 2009

First-level interconnects with slender columns, and processes of forming same

Sanka Ganesan; Richard J. Harries; Sujit Sharan


Archive | 2007

PACKAGED INTEGRATED CIRCUIT AND METHOD OF FORMING THEREOF

Sudarshan Rangaraj; Sanka Ganesan; Dongming He; Richard J. Harries; Sairam Agraharam


Archive | 2012

USING COLLAPSE LIMITER STRUCTURES BETWEEN ELEMENTS TO REDUCE SOLDER BUMP BRIDGING

Ameya Limaye; Richard J. Harries; Sandeep B. Sane

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