Young-rae Park

The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV/sub DS/, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.

High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond

For the first time, the DRAM device composed of 6F/sup 2/ open-bit-line memory cell with 80nm feature size is developed. Adopting 6F/sup 2/ scheme instead of customary 8F/sup 2/ scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F/sup 2/ accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F/sup 2/, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V/sub th/ so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F/sup 2/ scheme. By adopting S-RCAT, V/sub th/ can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

Effects of nonionic surfactants on oxide-to-polysilicon selectivity during chemical mechanical polishing

The effects of surfactants on oxide-to-polysilicon selectivity during chemical mechanical polishing have been investigated. Slurries with nonionic surfactants such as Brij surfactants, polyethylene oxide (PEO), and ethylene oxide-propylene oxide-ethylene oxide triblock copolymer enhanced oxide-to-polysilicon polishing selectivity. Although a current conventional oxide slurry has a low oxide-to-polysilicon selectivity of 0.5:1, slurries with nonionic surfactants show a higher selectivity due to a combined effect of adsorption and interfacial adhesion of added nonionic surfactant molecules on the polysilicon surface. The oxide-to-polysilicon selectivity of the Brij surfactant added slurry displayed a stronger dependency on the hydrophile-lipophile-balance (HLB) value than the type of alkyl group or the chain length of surfactants. Especially, Brij52 with low HLB value gave an oxide-to-polysilicon selectivity of 9.3, which is 17 times higher than the selectivity of a commercial oxide slurry. A high molecular weight polymeric surfactant such as PEO also gave a greater selectivity than a low molecular weight surfactant. In addition, slurries with nonionic surfactants reduce the final thickness variation effectively in damascene structure having a polysilicon stopping layer. The final thickness variation polished with the Brij52 added slurry was decreased to one fourth of that with the conventional oxide slurry only.

Analysis of Thermal Variation of DRAM Retention Time

Variation of DRAM retention time induced by thermal stress was investigated. Thermal activation energies (Ea) of sub-threshold leakage, junction leakage and GIDL (Gate Induced Drain Leakage) current of a DRAM cell were measured using the test vehicles. The values were compared with Ea of 1/tREF for the DRAM cell of which the retention time had been varied after a thermal stress. Ea of 1/tREF for the thermally degraded DRAM cell was in the range of that for GIDL current, while Ea for the normal DRAM cells with high retention time was in the range of Ea for junction leakage. It is insisted that the thermal degradation of retention time is induced by increase in GIDL current. The contributions of gate oxide/substrate interface states to the GIDL current are discussed