Sang-Uk Park

Characterization of Random Telegraph Signal Noise of High-Performance p-MOSFETs With a High-

The behavior of ID random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO2/TaN is experimentally investigated and discussed. The ID-RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of ID-RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (ΔID/ID) of the p-MOSFETs with high-k (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, ID-RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications.

k

In this work, new test structures are proposed to characterize the RTS (Random Telegraph Signal) noise of the CMOS image sensor. The RTS noise of the driver transistor and the source follower transistor, as well as the source follower block itself, are measured using the proposed test structures. The probability of monitoring the RTS noise of the driver transistor and the source follower transistor is 76 % and 52 %, respectively. However, the probability of the generation of the RTS noise for the source follower block is about 74 %. Therefore, it can be said that the driver transistor dominates the RTS noise of the source follower block.

Dielectric/Metal Gate

A novel test structure of bipolar junction transistors fabricated using CMOS technology is proposed for high-performance analog applications. The matching characteristics of collector current IC and current gain β of the proposed structure show improvement of about 31% and 24%, respectively, over those of the conventional structure, although the area of the proposed structure is smaller than that of the conventional structure. The proposed structure exhibits a decrease in collector current and current gain of less than 7.4% and 1.8%, respectively, compared with the conventional structure. The proposed test structure is highly promising for CMOS-based, high-performance, analog applications.

Decoupling of RTS noise in high density CMOS image sensor using new test structures

In this paper, the dependence of low-frequency (LF) noise, such as 1/f noise and random telegraph signal (RTS) noise, and the hot carrier reliability in n-channel metal–oxide–semiconductor field-effect transistors (NMOSFETs) on channel stress has been studied. The normalized noise power spectral density (SID /ID2) and RTS amplitude of NMOSFETs with compressive channel stress are greater than those with tensile channel stress because the active traps contributing to RTS noise with compressive stress are distributed closer to the Si/SiO2 interface. LF noise characteristics, as well as device performance are enhanced by introducing tensile channel stress to nanoscale NMOSFETs. However, it is shown that device degradation caused by tensile channel stress is greater than that caused by compressive channel stress under channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) stress conditions. Therefore, concurrent consideration of reliability and LF noise characteristics as well as dc device performance is necessary in channel strain engineering for next generation complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) especially for analog or mixed signal integrated circuit applications.

Novel BJT test structure for high-performance matching characteristics in CMOS-based analog applications

This article introduces the characterization of spin coated ZnO transparent conducting oxide on the flexible substrates. As a II-IV compound semiconductor, ZnO has a wide band gap of 3.37 eV with transparent properties. Due to this transparent properties, ZnO materials can be also employed as the transparent conducting electrode materials. Therefore, strong demands have been required for the transparent electrodes with low temperature processing and cheap cost. So, We will investigate the electrical property and optical transmittance of ZnO transparent conducting oxide through the 4-point probe resistivity meter, and ultraviolet-vis spectrometer Lamda 35, respectively.

Dependence of Hot Carrier Reliability and Low Frequency Noise on Channel Stress in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, PBTI characteristics of NMOSFETs with La incorporated HfSiON and HfON are compared in detail. The charge trapping model shows that threshold voltage shift () of NMOSFETs with HfLaON is greater than that of HfLaSiON. PBTI lifetime of HfLaSiON is also greater than that of HfLaON by about 2~3 orders of magnitude. Therefore, high charge trapping rate of HfLaON can be explained by higher trap density than HfLaSiON. The different de-trapping behavior under recovery stress can be explained by the stable energy for U-trap model, which is related to trap energy level at zero electric field in high-k dielectric. The trap energy level of two devices at zero electric field, which is extracted using Frenkel-poole emission model, is 1,658 eV for HfLaSiON and 1,730 eV for HfLaON, respectively. Moreover, the optical phonon energy of HfLaON extracted from the thermally activated gate current is greater than that of HfLaSiON.

The Characterization of Spin Coated ZnO TCO on the Flexible Substrates

In this article, we investigated the fabrication and characteristics of Pd germanide Schottky contacts on n-type Ge substrate. It is shown that the lowest sheet resistance and uniform Pd germanide can be obtained by a one step RTP at 400 °C for 30 sec. The proposed Pd germanide/nGe contact exhibited electron Schottky barrier height and work function of 0.565~0.577 eV and 4.695~4.702 eV, respectively. Therefore, the proposed Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.

Analysis of Positive Bias Temperature Instability Characteristic for Nano-scale NMOSFETs with La-incorporated High-k/metal Gate Stacks

In this study, thermal stability of Ni silicide on boron, BF2, and B18H22 implanted junctions is improved using Ni-Pd(5%) alloy target. The proposed Ni-Pd(5%)/TiN structure enabled the maintenance of low sheet resistance during the RTP and post silicidation annealing than conventional Ni/TiN structure. The improvement of Ni silicide properties is analyzed to be due to the formation of Pd2Si of which peaks were confirmed by XRD data, which indicates the reaction has substantially occurred during the RTP and post silicidation annealing. Moreover, it is also shown that the proposed Ni-Pd(5%)/TiN is efficient in reducing the reverse leakage current as well as improving the thermal stability of ultra shallow junction with B18H22 implantation.

Study on palladium germanide on Ge-on-Si substrate for nanoscale Ge channel Schottky barrier MOSFETs

In this paper, we investigated the dependence of device performance and hot carrier lifetime on the channel direction of PMOSFET. ID.sat vs. IOff characteristic of PMOSFET with channel direction is greater than that with channel direction because carrier mobility of channel direction is greater than that of channel direction. However, hot carrier lifetime for channel direction is much lower than that with channel due to the greater impact ionization rate in the channel direction. Therefore, concurrent consideration of reliability characteristics and device performance is necessary for channel strain engineering of MOSFETs.