Yi- Jung

Characterization of Random Telegraph Signal Noise of High-Performance p-MOSFETs With a High-

The behavior of ID random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO2/TaN is experimentally investigated and discussed. The ID-RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of ID-RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (ΔID/ID) of the p-MOSFETs with high-k (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, ID-RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications.

k

In this paper, the dependence of negative bias temperature instability (NBTI) and low-frequency noise characteristics on the various nitrided gate oxides is reported. The threshold voltage shift (ΔVT) under NBTI stress for thermally nitrided oxide (TNO) was greater than that of plasma nitrided oxide (PNO), whereas the slopes of ΔVT versus stress time for PNO were similar to those for TNO. The flicker noise (1/f noise) characteristic of PNO was better than that of TNO by about 1 order of magnitude, although the 1/f noise of PNO showed almost the same dependence on the frequency as that of TNO. The carrier number fluctuation model due to the trapping and detrapping of electrons in oxide traps was found to be a dominant mechanism of flicker noise. The probability of the generation of drain current random telegraph signal (ID–RTS) noise shows similar values (70–78%) for all nitrided oxides, which shows that the generation of RTS noise is not greatly affected by the nitridation method or nitrogen concentration.

Dielectric/Metal Gate

In this work, new test structures are proposed to characterize the RTS (Random Telegraph Signal) noise of the CMOS image sensor. The RTS noise of the driver transistor and the source follower transistor, as well as the source follower block itself, are measured using the proposed test structures. The probability of monitoring the RTS noise of the driver transistor and the source follower transistor is 76 % and 52 %, respectively. However, the probability of the generation of the RTS noise for the source follower block is about 74 %. Therefore, it can be said that the driver transistor dominates the RTS noise of the source follower block.

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal--Oxide--Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

A novel test structure of bipolar junction transistors fabricated using CMOS technology is proposed for high-performance analog applications. The matching characteristics of collector current IC and current gain β of the proposed structure show improvement of about 31% and 24%, respectively, over those of the conventional structure, although the area of the proposed structure is smaller than that of the conventional structure. The proposed structure exhibits a decrease in collector current and current gain of less than 7.4% and 1.8%, respectively, compared with the conventional structure. The proposed test structure is highly promising for CMOS-based, high-performance, analog applications.

Decoupling of RTS noise in high density CMOS image sensor using new test structures

Low frequency noise has become one of the major issues for an analog mixed signal and RF (radio frequency) circuits [1]. Previous studies have extensively analyzed drain/gate bias and temperature dependence of 1/f (flicker) noise in a strong inversion region [2, 3], whereas 1/f noise in a sub-threshold region has been investigated very little. The demand for low power consumption has increased due to the development of single battery cell phones. Hence, to reduce the dynamic power consumption of CMOS circuits, threshold voltage must be scaled down without degrading circuit speed or operating logic noise margins. Although Vth scaling is limited by the off-current and static power consumption constraints, a constant substrate biasing technique is used with standard CMOS technology to improve the performance of CMOS circuits. As this technique is used in analog-integrated circuits, such as current mirror and VCO (voltage controlled oscillator), the dependence of 1/f noise characteristics on body bias need to be analyzed. In addition, the noise characteristic of MOSFETs at high temperature is important for analog circuits because the analog circuits are more sensitive to temperature [4, 5]. However, there was little study on the noise characteristics concurrently considering the body bias and temperature. In this study, 1/f noise characteristics of NMOSFET were investigated for various body bias and temperature in a sub-threshold region.

Novel BJT test structure for high-performance matching characteristics in CMOS-based analog applications

In this paper, the dependence of low-frequency (LF) noise, such as 1/f noise and random telegraph signal (RTS) noise, and the hot carrier reliability in n-channel metal–oxide–semiconductor field-effect transistors (NMOSFETs) on channel stress has been studied. The normalized noise power spectral density (SID /ID2) and RTS amplitude of NMOSFETs with compressive channel stress are greater than those with tensile channel stress because the active traps contributing to RTS noise with compressive stress are distributed closer to the Si/SiO2 interface. LF noise characteristics, as well as device performance are enhanced by introducing tensile channel stress to nanoscale NMOSFETs. However, it is shown that device degradation caused by tensile channel stress is greater than that caused by compressive channel stress under channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) stress conditions. Therefore, concurrent consideration of reliability and LF noise characteristics as well as dc device performance is necessary in channel strain engineering for next generation complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) especially for analog or mixed signal integrated circuit applications.

Dependence of 1/f noise characteristics of NMOSFETs on body bias and temperature in sub-threshold region

In this paper, matching characteristic of MIM (metal-insulator-metal) capacitor with (AHA) structure is analyzed. The floating gate capacitance measurement technique (FGMT) was used for analysis of matching characteristic of the MIM capacitors in depth. It was shown that matching coefficient of AHA MIM capacitor is 0.331% which is appropriate for application to analog/RF integrated circuits. It was also shown that the matching coefficient has a more strong dependence on the width than length of MIM capacitor.

Dependence of Hot Carrier Reliability and Low Frequency Noise on Channel Stress in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, thermal stability of palladium germanide (Pd germanide) is analyzed for high performance Schottky barrier germanium metal oxide semiconductor field effect transistors (SB Ge-MOSFETs). Pd germanide Schottky barrier diodes were fabricated on n-type Ge-on-Si substrates and the formed Pd germanide shows thermal immunity up to . The barrier height of Pd germanide is also characterized using two methods. It is shown that Pd germanide contact has electron Schottky barrier height of 0.569~0.631 eV and work function of 4.699~4.761 eV, respectively. Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.

Analysis of Matching Characteristics of MIM Capacitors with Al 2 O 3 /HfO 2 /Al 2 O 3

In this paper, PBTI characteristics of NMOSFETs with La incorporated HfSiON and HfON are compared in detail. The charge trapping model shows that threshold voltage shift () of NMOSFETs with HfLaON is greater than that of HfLaSiON. PBTI lifetime of HfLaSiON is also greater than that of HfLaON by about 2~3 orders of magnitude. Therefore, high charge trapping rate of HfLaON can be explained by higher trap density than HfLaSiON. The different de-trapping behavior under recovery stress can be explained by the stable energy for U-trap model, which is related to trap energy level at zero electric field in high-k dielectric. The trap energy level of two devices at zero electric field, which is extracted using Frenkel-poole emission model, is 1,658 eV for HfLaSiON and 1,730 eV for HfLaON, respectively. Moreover, the optical phonon energy of HfLaON extracted from the thermally activated gate current is greater than that of HfLaSiON.

Analysis of Thermal Stability and Schottky Barrier Height of Pd Germanide on N-type Ge-on-Si Substrate

We studied on the electro-optic characteristics and dynamic stability according to an undesirably defined pretilt angle induced in high step coverage of pixel area for the Twisted Nematic (TN) / Fringe-Field Switching (FFS) mode. In case of the TN mode, LC directors twist reversely near the edges of thin-film-transistor and black matrix where the pretilt angle of the LC is not well defined. Therefore, the voltage-dependent dynamics of the LC in TN mode is unstable and shows the bad electro-optic characteristics. On the other hand, in case of the FFS mode, the LCs are twisted parallel to the bottom substrate by fringe electric field and the electro-optic characteristic is not influenced by the pretilt angle of the LC which is not well defined.