Yi-Sun Chung

Characterization of Random Telegraph Signal Noise of High-Performance p-MOSFETs With a High-

The behavior of ID random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO2/TaN is experimentally investigated and discussed. The ID-RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of ID-RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (ΔID/ID) of the p-MOSFETs with high-k (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, ID-RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications.

k

In this paper, the dependence of negative bias temperature instability (NBTI) and low-frequency noise characteristics on the various nitrided gate oxides is reported. The threshold voltage shift (ΔVT) under NBTI stress for thermally nitrided oxide (TNO) was greater than that of plasma nitrided oxide (PNO), whereas the slopes of ΔVT versus stress time for PNO were similar to those for TNO. The flicker noise (1/f noise) characteristic of PNO was better than that of TNO by about 1 order of magnitude, although the 1/f noise of PNO showed almost the same dependence on the frequency as that of TNO. The carrier number fluctuation model due to the trapping and detrapping of electrons in oxide traps was found to be a dominant mechanism of flicker noise. The probability of the generation of drain current random telegraph signal (ID–RTS) noise shows similar values (70–78%) for all nitrided oxides, which shows that the generation of RTS noise is not greatly affected by the nitridation method or nitrogen concentration.

Dielectric/Metal Gate

A novel test structure of bipolar junction transistors fabricated using CMOS technology is proposed for high-performance analog applications. The matching characteristics of collector current IC and current gain β of the proposed structure show improvement of about 31% and 24%, respectively, over those of the conventional structure, although the area of the proposed structure is smaller than that of the conventional structure. The proposed structure exhibits a decrease in collector current and current gain of less than 7.4% and 1.8%, respectively, compared with the conventional structure. The proposed test structure is highly promising for CMOS-based, high-performance, analog applications.

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal--Oxide--Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

A novel structure is proposed to improve the matching characteristics of bipolar junction transistor (BJT) based on CMOS technology for high performance analog circuit applications. This paper includes the analysis of electrical and matching characteristics in collector current density (JC), base current density (JB) and current gain (β). Although the collector current density JC of the proposed structure is similar to that of the conventional structure, the base current density JB is lower than that of conventional structure, which results in higher current gain. The matching characteristics of the collector current density and the current gain of the proposed structure showed improvement of about 12.22% and 36.43%, respectively compared with the conventional structure.

Novel BJT test structure for high-performance matching characteristics in CMOS-based analog applications

In this paper, the 1/f noise characteristics of n-channel MOSFET (NMOSFET) and p-channel MOSFET (PMOSFET) are analyzed in depth as a function of body bias. The normalized drain current noise, S ID /I D 2 showed strong dependence on the body bias in the sub-threshold region for both NMOSFET and PMOSFET, and NMOSFET showed stronger dependence than PMOSFET on the body bias. On the contrary, both of NMOSFET and PMOSFET do not exhibit the dependence of S ID /I D 2 on body bias in strong inversion region, although the noise mechanisms of two MOSFETs are different from each other.

A novel BJT structure for high- performance analog circuit applications

Metal-insulator-metal (MIM) Capacitors are widely used for radio frequency (RF) and analog mixed signal (AMS) circuits, and dynamic random access memory (DRAM) applications [1]. Although high capacitance density of MIM capacitor for RF and AMS circuits is required to reduce the chip size and system cost, the conventional dielectric materials, such as SiO 2 and Si 3 N 4 , as the thickness of dielectric scales down, emerge as key limitations due to high leakage current and reliability issues. High-k (HK) dielectric, such as HfO 2 , Al 2 O 3 , ZrO 2 , Ta 2 O 5 , and La 2 O 3 , is necessary to achieve the high capacitance density and to reduce the leakage current [2]. Among the various HK dielectric candidates, hafnium-based MIM capacitors are widely used due to their high capacitance density, good thermal stability, and high band gap [3]. However, HK dielectric for MIM capacitors induces high voltage linearity and poor reliability characteristics after electrical stress, due to defects in the metal-insulator interface. The reliability characteristic of MIM capacitor under electrical stress is related to the injected charge in the interface of HK dielectrics [4]. These degradations cause the distortion of MIM capacitors, which limits the performance of the RF and AMS circuits. Hence, an accurate analysis of the degradation of MIM capacitor under electrical stress is required in order to stabilize these characteristics. Moreover, various kinds of voltage shape can be applied to the MIM capacitors. However, there was little study on the effect of stress voltage type on the reliability of advanced MIM capacitors. In this work, reliability of MIM capacitor with high capacitance density was analyzed using three kinds of voltage stress; constant voltage stress (CVS), unipolar voltage and bipolar voltage stresses.

Dependence of the 1/f Noise Characteristics of CMOSFETs on Body Bias in Sub-threshold and Strong Inversion Regions

As the scaling of silicon (Si) CMOS device continues, new materials such as SiGe, Ge, group III-V semiconductor, CNT, and Graphene are introduced due to the limit of Si CMOS such as short channel effects (SCE) and mobility degradation. Ge metal oxide semiconductor field effect transistors (Ge-MOSFETs) have received a lot of attention because of their higher carrier mobility compared with Si. Other advantages of Ge are its lower melting point and lower thermal budget processes compared with Si. However, Ge technology also has disadvantage. Currently, Ge MOSFET devices face several challenges such as water solubility, poor stability of germanium oxides, and small band gap [1–2]. The smaller band gap of Ge leads to higher off-current in MOSFET due to its higher source/drain junction leakage and worse SCE.

Characterization of Al 2 O 3 -HfO 2 -Al 2 O 3 sandwiched MIM capacitor under DC and AC stresses

In this paper, we investigated the dependence of device performance and hot carrier lifetime on the channel direction of PMOSFET. ID.sat vs. IOff characteristic of PMOSFET with channel direction is greater than that with channel direction because carrier mobility of channel direction is greater than that of channel direction. However, hot carrier lifetime for channel direction is much lower than that with channel due to the greater impact ionization rate in the channel direction. Therefore, concurrent consideration of reliability characteristics and device performance is necessary for channel strain engineering of MOSFETs.