Sanjay Kapasi

Interlayer self-aligning process for 22nm logic

Line/space dimensions for 22nm logic are expected to be ~35nm at ~70nm pitch for metal 1. However, the contacted gate pitch will be ~90nm because of contact-to-gate spacing limited by alignment. A process for self-aligning contact to gates and diffusions could reduce the gate pitch and hence directly reduce logic and memory cells sizes. Self-aligned processes have been in use for many years. DRAMs have had bit-line and storage-node contacts defined in the critical direction by the row-lines. More recently, intra-layer self-alignment has been introduced with spacer double patterning, in which pitch division is accomplished using sidewall spacers defined by a removable core.[1] This approach has been extended with pitch division by 4 to the 7nm node.[2] The introduction of logic design styles which use strictly one-directional lines for the critical levels gives the opportunity for extending self-alignment to inter-layer applications in logic and SRAMs. Although Gridded Design Rules have been demonstrated to give area-competitive layouts at existing 90, 65, and 45nm logic nodes while reducing CD variability[3], process extensions are required at advanced nodes like 22nm to take full advantage of the regular layouts. An inter-layer self-aligning process has been demonstrated with both simulations and short-loop wafers. An extension of the critical illumination step for active and gate contacts will be described.

Source-mask selection using computational lithography incorporating physical resist models

The RET selection process, for 32 nm and 22 nm technology nodes, is becoming evermore complex due to an increase in the availability of strong resolution enhancements (e.g., polarization control, custom exotic illuminators, hyper NA). Lithographers often select the illuminator geometries based on analyzing aerial images for a limited set of structures. However, source-shape geometries optimized using this methodology is not always optimal for other complex patterns. This leads to critical hot-spots on the final wafer images in form of bridges and gaps. Lithographers would like to analyze the impact of selected source-shape on wafer results for the complex patterns before running the physical experiments. Physics based computational lithography tools allow users to predict the accurate wafer images. This approach allows users to run large factorial experiments for simple and complex designs without running physical experiments. In this study, we will analyze the lithographic performance of simple 1D patterns using aerial image models and physical resist models with calibrated resist parameters1,2,3,4 for two commercial resists. Our goal is to determine whether physical resist models yield a different optimal solution as compared to the aerial image model. We will explore several imaging parameters - like Numerical Aperture (NA), source geometries (Annular, Quadrupole, etc.), illumination configurations and anchor features for different sizes and pitches. We will apply physics based OPC and compute common process windows using physical model. In the end, we will analyze and recommend the optimal source-mask solution for given set of designs based on all the models.

The Causes of Horizontal-Vertical (H-V) Bias in Optical Lithography: Dipole Source Errors

Horizontal-Vertical (H-V) bias is the systematic difference in linewidth between closely located horizontally and vertically oriented resist features that, other than orientation, should be identical. There are two major causes of H-V bias: astigmatism, which causes an H-V bias that varies through focus, and illumination source errors such as telecentricity error. In this paper, the effects of simple dipole source errors upon H-V bias and placement error through focus are explored through simulation.

The impact of resist model on mask 3D simulation accuracy beyond 40nm node memory patterns

Beyond 40nm lithography node, mask topograpy is important in litho process. The rigorous EMF simulation should be applied but cost huge time. In this work, we compared experiment data with aerial images of thin and thick mask models to find patterns which are sensitive to mask topological effects and need rigorous EMF simulations. Furthur more, full physical and simplified lumped (LPM) resist models were calibrated for both 2D and 3D mask models. The accuracy of CD prediction and run-time are listed to gauge the most efficient simulation. Although a full physical resist model mimics the behavior of a resist material with rigor, the required iterative calculations can result in an excessive execution time penalty, even when simulating a simple pattern. Simplified resist models provide a compromise between computational speed and accuracy. The most efficient simulation approach (i.e. accurate prediction of wafer results with minimum execution time) will have an important position in mask 3D simulation.

Source-mask selection using computational lithography: further investigation incorporating rigorous resist models

Recent publications have emphasized the criticality of computational lithography in source-mask selection for 32 and 22 nm technology nodes. Lithographers often select the illuminator geometries based on analyzing aerial images for a limited set of structures using computational lithography tools. Last year, Biafore, et al1 demonstrated the divergence between aerial image models and resist models in computational lithography. In a follow-up study2, it was illustrated that optimal illuminator is different when selected based on resist model in contrast to aerial image model. In the study, optimal source shapes were evaluated for 1D logic patterns using aerial image model and two distinct commercial resist models. Physics based lumped parameter resist model (LPM) was used. Accurately calibrated full physical models are portable across imaging conditions compared to the lumped models. This study will be an extension of previous work. Full physical resist models (FPM) with calibrated resist parameters3,4,5,6 will be used in selecting optimum illumination geometries for 1D logic patterns. Several imaging parameters - like Numerical Aperture (NA), source geometries (Annular, Quadrupole, etc.), illumination configurations for different sizes and pitches will be explored in the study. Our goal is to compare and analyze the optimal source-shapes across various imaging conditions. In the end, the optimal source-mask solution for given set of designs based on all the models will be recommended.

The divergence of image and resist process metrics

It is common for computational lithography optimization to be performed using the metrics of the simulated aerial image (AI). Using the AI, the wafer-level CD can be estimated in a number of ways, such as thresholding with or without convolution of the AI with a point-spread function. The assumption of such an approach is that the relationship between the AI CD and the resist CD response is linear. However, the properties of resist reaction-diffusion-development yield a process which is highly non-linear. For example, it is well-known that different photoresists produce a different lithographic response to the same aerial image; isofocality, depth-of-focus, exposure latitude, MEF etc. all vary from one resist to another for the same projection optics and mask. Several publications have demonstrated that a well-calibrated physical resist model can be extrapolated to accurately predict the CD and profile response of the resist process over a wide range of optical and process conditions1-4. In this work, the divergence in performance between resist processes and the projected image-in-the resist is explored through simulation.