Sanjay S. Natarajan

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors

A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um Ioff. PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported.

A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum2 cell size, containing >1.9 billion transistors.

A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum, respectively, have been achieved at 1.2V and off-state leakage of 100 pA/mum. Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression schemes are also discussed

An advanced low power, high performance, strained channel 65nm technology

An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing

A classifier neural net with complex-valued weights and square-law nonlinearities

Abstract A new pattern recognition classifier neural net (NN) is described that uses complex-valued weights and square-law nonlinearities. We show that these weights and nonlinearities inherently produce higher-order decision surfaces and thus we expect better classification performance (Pc). We refer to this as the piecewise hyperquadratic neural net (PQNN) because each hidden layer neuron inherently provides a hyperquadratic decision surface and the combination of neurons provides piecewise hyperquadratic decision surfaces. We detail the learning algorithm for this NN and provide initial results on synthetic data showing its advantages over the back propagation and other NNs. We also note a new technique to provide improved classification results when there are significantly different numbers of samples per class.

Neural net selection of features for defect inspection

An artificial neural network (ANN) fed with optically generated features is applied to IC inspection. The data used are characters with defects in them that model those expected in IC patterns. The ANN is used in training to select the best features. This results the required number of neurons needed during defect testing. Simulation results are provided for four types of defects using optical Fourier Wedge-Ring (WR) sampled Fourier and Hough feature spaces.

Piecewise quadratic optical neural network

A neural network pattern classifier is presented. Its decision boundaries are formed from segments of conic sections which allows it to achieve improved performance over piecewise linear neural network classifiers, such as our earlier adaptive clustering neural network (ACNN). We discuss an optical realization that uses complex-valued weights, optical intensity detectors, and an additional input neuron to achieve piecewise conic decision surfaces (rather than the piecewise linear surfaces that the ACNN produces).© (1993) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Piecewise quadratic neural network for pattern classification (Proceedings Only)

A neural network pattern classifier is presented. Its decision boundaries are formed from segments of conic sections which allows it to achieve improved performance over piecewise linear neural network classifiers, such as our earlier adaptive clustering neural network (ACNN). We discuss an optical realization that uses complex-valued weights, optical intensity detectors, and an additional input neuron to achieve piecewise conic decision surfaces (rather than the piecewise linear surfaces that the ACNN produces).