Sarah H. Knickerbocker

50μm pitch Pb-free micro-bumps by C4NP technology

Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50 mum pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200 mm and 300 mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstrations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50 mum pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.

Viscosity of MgO-Al2O3-SiO2-B2O3-P2O5 cordierite-type glasses

Mesure entre 850 et 920°C de la viscosite de cinq compositions du systeme MgO−Al 2 O 3 −SiO 2 avec additions de B 2 O 3 et P 2 O 5

Development and Implementation of C4NP Technology for 300 mm Wafers

Considerable work is ongoing worldwide on developing lead-free solutions for electronics industry to meet the needs of RoHs requirements. This paper describes the development and implementation of lead-free C4 interconnects for 300 mm wafers using, C4NP technology at IBM with equipment partnership with Suss MicroTech Inc. Key process modules of C4NP technology are: (a) UBM pads fabrication using simple unit processes in back end of the line semiconductor manufacturing facility, (b) Solder melt filling of glass molds with cavities in solder fill tool and inspection, (c) C4 bump transfer to UBM pads on wafers using vaporized flux process in solder transfer tool, (d) Final inspections and electrical tests. This process technology for C4 bumping eliminates the need for solder or solder alloy plating and provides wider latitude for selecting solder composition. For example, solders can be selected for improved mechanical properties and, or low alpha emission requirements. This can be accomplished by simple changing of mold fill head. Primary efforts of this study are focused on four key elements: (1) Development of unit processes for UBM pad patterning and solder transfer processing, (2) chip/organic laminate module builds, using industry standard bond and assembly processes, (3) selection of specific test vehicle wafers with 200 um pitch pads and over 1.25 million C4 bumps, and (4) extensive reliability testing of modules with JDEC and IBM internal standards. Modules with test vehicle chips as well as product chips have shown excellent reliability data, comparable to that of high lead electroplated C4 bumps, and meet application requirements. In order to assess manufacturing robustness and yields, sector partitioning studies were undertaken to understand the effects of unit process windows and defect densities. Results show that C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Technology qualification studies have been successfully completed. Thus, enabling the path for manufacturing ramp up. This technology is extendable to higher density C4 interconnects and product qualifications studies on C4 bumps on 150 um pitch are ongoing. IBM is adapting this technology for 300 mm lead-free applications.

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Controlled collapse chip connection - new process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300 mm Pb-free solder bumped wafers. Both 200 mum and 150 mum pitch products have been qualified and are currently ramping up volume production. Extendibility of C4NP to 50 mum ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.

Sinterable glass-ceramics for high-performance substrates

Glasses in the MgO-Al/sub 2/O/sub 3/-SiO/sub 2/ system were developed for use in fabricating multilayer substrates with copper thick-film metallurgy. These glasses sintered dense in the glassy state and subsequently crystallized to yield glass-ceramics with alpha -cordierite as the principal crystalline phase. An understanding of the factors governing sintering, crystallization, and microstructure development has been obtained. The range of thermal expansion coefficients, dielectric constants, and flexural strengths of the sintered glass-ceramics met the requirements for a high-performance, multilayer substrate.<<ETX>>

End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications

The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level “device” side copper wiring, with line space (L/S) of ≤ 2.5 μm, built using damascene techniques, a 55 μm glass core with through glass vias (TGVs), and multiple UBM levels finished with tin silver (SnAg) C4 bumps. The 300mm TGV wafers are processed on existing silicon wafer manufacturing equipment following established, integrated silicon process flows. Once fully processed, the glass wafers are diced, and the interposer joined to a ceramic carrier by mass reflow. Sub-assemblies are then underfilled, the top die attached, and lidding completed. The final assemblies are tested to evaluate performance of chip to chip interconnects, chip-to-package (through interposer) interconnects, and chip-to-PCB (through interposer and package) interconnects. Results of loss vs frequency measurements are compared, for the glass interposer against the existing silicon interposer results.

Selective nickel and gold plating for enhanced wire bonding technology

Nickel and gold are electrodeposited on wire bond pads by a newly developed selective plating process in which plating is done without photoresist. The gold terminal metal offers exciting advantage over the traditional aluminum metallurgy. The unique self-encapsulating structure of gold and nickel over copper seed is illustrated. The plating tool, process control and thickness uniformity are described. We have evaluated this structure with probing, aging and stress under high temperature (200degC) in conjunction with bonding. We also varied the bonding conditions to allow a wider choice of inter-level dielectrics and structure/device placement under pads. All the data shows that this is a viable alternative to the current process of record