Roger A. Quon

Cobalt interconnect on same copper barrier process integration at the 7nm node

Cobalt and copper interconnects with identical barrier and CMP processes were formed on ultra-low k (ULK) dielectric films at the 7nm node. Divot-free Co and Cu interconnects are demonstrated using the same CMP process. Co-filled dual damascene interconnects show high line yields with similar via resistance values compared to Cu. Co line resistance measures three times higher resistance than Cu. The resistivity of Co and Cu lines is calculated by measuring line resistance and cross-sectional area by transmission electron microscopy (TEM). Measured via resistance of the dual damascene Co-filled via is only 10% higher than the Cu-filled via control. Thus by scaling or even eliminating traditional Cu barriers in the via, Co can be a valid Cu replacement candidate for via fill.

A first-principles analysis of ballistic conductance, grain boundary scattering and vertical resistance in aluminum interconnects

We present an ab initio evaluation of electron scattering mechanisms in Al interconnects from a back-end-of-line (BEOL) perspective. We consider the ballistic conductance as a function of nanowire size, as well as the impact of surface oxidation on electron transport. We also consider several representative twin grain boundaries and calculate the specific resistivity and reflection coefficients for each case. Lastly, we calculate the vertical resistance across the Al/Ta(N)/Al and Cu/Ta(N)/Cu interfaces, which are representative of typical vertical interconnect structures with diffusion barriers. Despite a high ballistic conductance, the calculated specific resistivities at grain boundaries are 70-100% higher in Al than in Cu, and the vertical resistance across Ta(N) diffusion barriers are 60-100% larger for Al than for Cu. These results suggest that in addition to the well-known electromigration limitations in Al interconnects, electron scattering represents a major problem in achieving low interconnect line resistance at fine dimensions.We present an ab initio evaluation of electron scattering mechanisms in Al interconnects from a back-end-of-line (BEOL) perspective. We consider the ballistic conductance as a function of nanowire size, as well as the impact of surface oxidation on electron transport. We also consider several representative twin grain boundaries and calculate the specific resistivity and reflection coefficients for each case. Lastly, we calculate the vertical resistance across the Al/Ta(N)/Al and Cu/Ta(N)/Cu interfaces, which are representative of typical vertical interconnect structures with diffusion barriers. Despite a high ballistic conductance, the calculated specific resistivities at grain boundaries are 70-100% higher in Al than in Cu, and the vertical resistance across Ta(N) diffusion barriers are 60-100% larger for Al than for Cu. These results suggest that in addition to the well-known electromigration limitations in Al interconnects, electron scattering represents a major problem in achieving low interconnect l...

Microstructure modulation for resistance reduction in copper interconnects

Microstructure variation with post-patterning dielectric aspect ratio (AR) and post-plating annealing temperature has been investigated in Cu narrow wires. As compared to the conventional annealing at 100 ◦C for a feature AR of 2.6, both elevated temperature anneals and reduced AR structures modulated Cu microstructure, which then resulted in a reduced rate of electrical resistivity increase with area scaling and an increased electromigration resistance in the Cu narrow wires.

Pre-liner dielectric nitridation for resistance reduction in copper interconnects

Adhesion tests, parametric measurements, and reliability evaluations of an in-situ pre-liner dielectric nitridation process prior to pure Ta liner deposition were carried out, to evaluate the feasibility of reducing via resistance in BEOL Cu/low-k interconnects. Replacing TaN/Ta with Ta in the conventional liner stack reduces Cu via resistance, while the nitridation treatment maintains Cu interconnect integrity and reliability.

Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits

This paper demonstrates the first reliable and low cost airgap BEOL technology, generated at extremely tight dimensions (48 nm pitch) in Cu/ULK. This provides 20% nested-line capacitance reduction relative to the ungapped Cu/ULK baseline. This result is of critical importance, as it validates that airgaps can be extended down to ultrafine wire levels, such as for the 10 nm technology node. Current technologies implement airgaps only at fat-wire levels; however, a significant enhancement in chip performance can be gained by including airgaps in the finest wiring levels as well. To achieve this, we benefitted from several elements which address various process, integration, and reliability challenges associated with airgap formation at such small dimensions. We present data and explanations of these solutions, and their impacts on yield, performance, defectivity and reliability (EM and TDDB).

Optimization of porous ultra low-κ dielectrics (κ ≤ 2.55) for 28nm generation

There is an ongoing need in the microelectronics industry to increase circuit density in multilevel back-end-of line (BEOL) interconnects to improve the operating speed and reduce power consumption. One way to maintain capacitance-resistance (RC) performance, without de grading yield or reliability is through introduction of porous ultra low-κ materials (ULK) as interlevel dielectrics (ILD). This paper presents the ability to tune ULK films through simple processing optimization steps to meet the specific integration requirements. Balancing composition of the film to minimize damage needs to be coupled with improving mechanical integrity for packing compatibility.