Kamalesh K. Srivastava

C4NP technology: Manufacturability, yields and reliability

As a part of IBM movement from Pb-rich solders to Pb-free solder, a new low cost process has been developed to deposit the solder to a capture, or under bump metal (UBM) pad, with Suss MicroTech Inc as the equipment partner. The controlled collapsed chip connection new process (C4NP) has moved, over the last 2 years, from development into manufacturing for 300 mm wafers. During this transition, a great number of process improvements have resulted in high fabrication yields. Manufacturing robustness has been achieved by clearly identifying the processes which affect the C4 structural integrity. The solder composition has been optimized to improve its mechanical properties as well as low alpha emission rate requirement. Sector partitioning methodology was used to obtain root cause for various defects which then, through replication studies, were confirmed. Key process improvements in the capture pad build, mold fabrication, and mold fill tool have been accomplished as the process has matured. Thermal undercut was identified as a mechanism of Cu seed consumption when no top Cu was available on top of the Ni UBM. C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Yield learning model shows a 15% defect reduction per month since the start of the C4NP program. Technology qualification for 300 mm wafers with 200um and 150 um pitch Pb-free C4 bumps has been successfully completed.

Effects of parylene coating on the thermal fatigue life of solder joints in ceramic packages

A study was undertaken to determine the effectiveness of a thin layer (9.4 mu m in thickness) of a chemical vapor deposited polymer, parylene, in enhancing the solder lifetime of a ceramic package containing large-DNP (distance to neutral point) test chips. Both coated and uncoated (control) packages with chips joined via C4 Pb/Sn solder technology were thermally cycled near room temperature and liquid nitrogen temperature (-196 degrees C) until solder failure was first noticed in coated packages. The number of cycles to first failure for coated packages was found to be twice the corresponding number for uncoated packages. To interpret this twofold solder life enhancement, an elasto-plastic finite-element model was developed. Based on the results provided by this model and a low-temperature solder lifetime model, it was possible to attribute the extended solder life to the modification of the strain and stress fields in the solder joints by the parylene coating. The model also suggests that the solder life can be prolonged significantly with a parylene coating as thin as 3 mu m. >

The impact of process parameters on the fracture of device structures during chip joining on organic laminates

Detailed observations of the impact of various process parameters on the fracture of brittle structures in low-k dielectric flip chips assembled on organic laminates using lead-free metallurgies are reported. Specifically, a simple model is first presented to evaluate the stresses transmitted to the chip back end of line structures which are susceptible to failure during the reflow at chip joining. These stresses are regulated by creep deformation, so that damage to the chip can be controlled by carefully engineering the creep properties of the solder joints. We introduce new experimental techniques to monitor the creep behaviour of the joints during the reflow. In particular, we describe the use of a laser interferometer technique to monitor the chip curvature with a high sampling rate (few Hz) throughout the reflow. It is shown that these measurements can be used to predict the likelihood of causing brittle fracture in the chip structures. Additionally, we present electron backscatter diffraction (EBSD) data for the microstructure of a large number of solder joints. Using a combination of these theoretical and experimental observations, we derive a complete phenomenology for brittle fractures in the chip during the reflow. The creep-limited stresses are a strong function of solder joint plastic strain rates, which in turn are a strong function of cooling rates during the reflow. Creep properties are also a strong function of the solder metallurgy: reducing the silver content in the SnAgCu alloys results in a higher propensity for creep and correspondingly lower stresses. Thermal treatments at high temperature, such as annealing, can affect the characteristics of the intermetallic compounds, resulting in different creep properties. These trends are observed as the limiting behaviour of the relatively large number of solder joints in typical flip chip packages, but due to the small size of the solder joints (approximately 100 mum in diameter), significant variability is observed from joint to joint in the interconnect array. We link this variability to the joint microstructure by showing that the size and orientation of the few grains generally forming these joints influence the risk to cause damage in the chip.

Parylene encapsulation of ceramic packages for liquid nitrogen application

A study was undertaken to determine the effectiveness of a thin layer (9.4 mu m in thickness) of a chemical-vapor-deposited polymer, Parylene, in enhancing the solder lifetime of IBM ceramic packages containing large-DNP (distance to neutral point) test chips during liquid-nitrogen operation. Coated and uncoated (control) packages with chips joined using C4 (controlled collapse chip connection) Pb/Sn solder technology were thermally cycled between near room temperature and liquid-nitrogen temperature. At every 50 or 100 cycles, the electrical resistances of solder joints were measured at room temperature for the nondestructive detection of solder failures based on a solder electrical-resistance criterion. The thermal cycling experiment and electrical measurement were continued until solder failure was first noticed in coated packages. The number of cycles to first failure was twice the corresponding number for uncoated packages. To help interpret this two-fold solder-life enhancement associated with parylene, an elastoplastic finite-element model was developed and used to determine the thermal strain and stress distributions near failed solder joints for coated and uncoated packages during thermal cycling. Based on the results provided by this model and a low-temperature solder lifetime model, the extended solder life was attributed to the ability of Parylene to modify the strain and stress fields in the solder joint as well as to its barrier and conformal-coating properties.<<ETX>>

Chip to carrier C4 technology challenges with Pb free solders

IBMpsilas C4 interconnection technology has continuously evolved over a period of forty years, i.e. from evaporation, to electroplating to C4NP, a C4 New Process. IBMpsilas initial C4NP efforts are focused on Sn-based Pb-free solder technology, in line with client requirements. Currently, all IBM bumped lead-free C4s are produced using the C4NP technology. Sn-based lead-free solders pose unique challenges because of higher microhardness and anisotropy of the tin crystalline structure, as compared to Pb-based solders. The simultaneous design requirements of increased power and current density, increased I/O counts and larger chips, and weak BEOL structure with low-k or ultra-low-k dielectric, demand a careful material interaction optimization between under bump metallurgy (UBM), bump solder, laminate solder, and laminate surface finish. In this paper, we will be discussing the challenges and some solutions of lead-free C4 bumping in terms of mechanical and thermo-electromigration.

Selective nickel and gold plating for enhanced wire bonding technology

Nickel and gold are electrodeposited on wire bond pads by a newly developed selective plating process in which plating is done without photoresist. The gold terminal metal offers exciting advantage over the traditional aluminum metallurgy. The unique self-encapsulating structure of gold and nickel over copper seed is illustrated. The plating tool, process control and thickness uniformity are described. We have evaluated this structure with probing, aging and stress under high temperature (200degC) in conjunction with bonding. We also varied the bonding conditions to allow a wider choice of inter-level dielectrics and structure/device placement under pads. All the data shows that this is a viable alternative to the current process of record

Technology Trends: Past, Present, and Future

Since the invention of flip chip technology by IBM about 40 years ago, there has been a continuous need for increased I/O density. More recently fine pitch technology is being enabled in Pb-free through Cu pillar and Sn–Ag solders. Stiffer Pb-free interconnection coupled with fragile low-k dielectric materials imposes a significant challenge on first level packaging. In response to increased number of interconnections and higher performance needs, additional technologies are emerging, such as the following: fine pitch flip chip (<60 μm pitch) interconnections, 3D with and without TSV’s, liquid phase connections, and bond-on line. This introductory chapter covers these technologies and sets the stage for current and future flip chip technologies discussed throughout the book.