Satoru Isomura

A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

An LSI device incorporating a 36-kb RAM and a 1k-gate logic array and using a 0.8- mu m sidewall base contact structure (SICOS) transistor process and four-layer metallization, is described. RAM and peripheral logic have been included in one chip to reduce input/output delay and interconnection delay between the RAM and logic. The chip layout is shown together with the circuit schematic of the RAM macro. RAM address access waveforms are shown along with the waveform of a 21-stage ring oscillator. Major device characteristics are summarized.<<ETX>>

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.

A Flexible 0.18

Hitachis SiGe BiCMOS technology, which integrates 0.18 μm CMOS and a SiGe heterojunction bipolar transistor (HBT), does not degrade MOS or bipolar performance. The BiCMOS process is divided into blocks, and the ordering of their processing is optimized so that they do not interfere with each other. Low-thermal-budget SiGe HBT formation is achieved using a minimal-moisture-desorption oxide layer, thereby avoiding disturbing the CMOS process. This technology, which can also be applied to the 0.13 μm generation, has been used for applications ranging from high-speed ones like automotive radar and 40 Gbps optical communication to consumer ones like wireless.

\mu{\rm m}

In this paper, we describe an advanced wiring RC timing design techniques for the gigahertz era. Our new technique of wiring capacitance extraction makes it possible to calculate more than 1 M nets within 3 hours as accurately as carrying out net-by-net 3-D simulations. Furthermore, we introduced the timing window for estimating crosstalk effects on delay time so as to distinguish harmful nets from harmless nets and reduce surplus design guard-bands.