Katsumi Ogiue

Perspective on BiCMOS VLSIs

A high-performance BiCMOS technology (Hi-BiCMOS) and its applications to VLSIs are described. By combining bipolar and CMOS devices in unit circuits of VLSIs, Hi-BiCMOS provides both speed performance competitive with bipolar LSIs and integration density close to that of CMOS LSIs. Hi-BiCMOS technology has been successfully used for static RAMs, dynamic RAMs, and gate arrays. The effectiveness of its applications to some types of processors has also been examined by evaluating test chips. >

Advanced BiCMOS technology for high speed VLSI

This paper describes the high performance BiCMOS (Hi-BiCMOS) device technology and discusses the scalability to sub-micron. As the device structure is scaled down from 2 µm to 1.3 µm, BiCMOS circuit performance is improved by the factor of the scaling. By further scale down to 0.8 µm, a 0.27 ns gate delay in BiCMOS gate and 5.5 ns access time of 64kbit BiCNOS ECL RAN are expected.

13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology

The development is discussed for a 13-ns, 500-mW, 16K word/spl times/4-bit emitter-coupled logic (ECL) RAM using high-performance bipolar CMOS (Hi-BiCMOS) technology that combines a bipolar and a CMOS device on the same chip. The power dissipation of the RAM is about one half that of the conventional 64-kb bipolar ECL RAM. This high-speed, low-power RAM has been realized through a concept of a MOS-type memory cell, bipolar circuits, and a CMOS combination gate to allow for increased LSI integration.

High speed BiCMOS VLSI technology with buried twin well structure

Bipolar transistors of high cut off frequency (f_{T}=9GHz) and small size have been fabricated on the same chip with a standard CMOS using the buried twin well structure. 1.3 µm LDD CMOS FETs were formed in the thin epitaxial layer(1-1.5µm) with the buried twin well, without degrading the device characteristics of the MOS FET. Ring oscillators of the BiCMOS gate have been fabricated. A 0.4ns gate delay time at 0.6pF and 3.5 times larger driveability than that of the same area CMOS gate were obtained.

A 13ns/500mW 64Kb ECL RAM

This paper will cover the design of a 16K×4 SRAM which uses buried twin-well 2μm CMOS transistors and 4GHz cutoff frequency bipolar transistors. The circuit combines a high-resistance polysilicon - load NMOS memory cell with mixed MOS/bipolar periphery circuits to achieve ECL compatibility, 13ns access times and an operating power of 500mW at 40MHz.

Performance and structures of scaled-down bipolar devices merged with CMOSFETs

Fabricating BiCMOS test samples, performance and structures of 2 µm and scaled BiCMOS are evaluated. The developed BiCMOS processes realize almost the same device characteristics of bipolar and CMOS LSIs fabricated with the same lithographic technology. The intrinsic delays of BiCMOS and CMOS 2-NAND circuits are 0.5 ns and 0.4 ns respectively. The delay times are comparable with the bipolar ECL circuits. The BiCMOS technology makes it possible to fabricate high-speed, low-power dissipation, high-packing density LSIs by sharing the roles among them.

A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array

An ECL (emitter-coupled-logic) 512-kb BiCMOS SRAM (statistic random access memory) with 1-kG logic and using 0.8- mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is described. The RAM has 5-ns address access time and 2-ns write-pulse width. The logic gate has 150-ps propagation delay with 4-mW power dissipation. A RAM-with-logic configuration is adopted to eliminate interconnection delay between the RAM and peripheral logic and to facilitate a wide-bit RAM. The design rule dependence of the delay time of a three-input ECL OR/NOR gate and a two-input BiCMOS NAND gate is shown. On-chip address access times, under 5 ns from address latches to data-out latches at room temperature with a marching test pattern, are also shown. Major characteristics of the LSI are presented.<<ETX>>

A 7ns/350mW 64K ECL compatible RAM

A 64K×1 ECL RAM using 1.3μm bipolar-CMOS technology including bipolar transistor with a 7GHz cutoff frequency will be presented. Variable impedance and equalizing circuitry permit 7ns access time. Power dissipation is 350mW.

An 8 ns 256 K BiCMOS RAM

A 256 K word*1 bit emitter-coupled logic (ECL) RAM, which achieves an 8 ns address access time, less than 400 mW power consumption at 50 MHz operation, and 150 mW at standby mode, is presented. To achieve an address access time of less than 10 nss and high packing density, an advanced 1.0 mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is used. A 9 GHz bipolar transistor cutoff frequency, 0.26 ns ECL gate propagation delay time, and 0.35 ns BiCMOS gate have been obtained. A 1.0 mu m design rule permits layout of an NMOS memory cell with a high-resistance polysilicon load in 54.7 mu m/sup 2/ and a 4.09*8.60 mm/sup 2/ chip. High performance is achieved by an optimized circuit design using a new input buffer, a BiCMOS decoder, and a high-speed bipolar sense amplifier. An active pull-down emitter-follower circuit and a BiCMOS current mirror ECL-MOS level shift circuit improve input buffer delay to less than 1.8 ns. A power-down technique has been studied to reduce standby power. Some experimental results are presented. High-speed address access is observed over a wide operational range. >

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.